Instruction converting apparatus using parallel execution code

ABSTRACT

A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1 tA  unit field in the parallel execution code, and the long instruction is assigned to the s th  unit field to the (s+k−1) th  unit field in the same parallel execution code.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an instruction conversion apparatus, aprocessor, a storage medium storing parallel execution codes to which aplurality of instructions have been assigned, and a computer-readablestorage medium storing an instruction conversion program that generatessuch parallel execution codes. In particular, the invention relates to atechnique for decreasing the number of execution cycles and improvingcode efficiency by using parallel processing.

2. Description of the Background Art

In recent years, parallel processing methods have been widely used inthe development of microprocessors. Parallel processing refers to theexecution of a plurality of instructions in each machine cycle. Examplesof classic parallel processing techniques are superscalar methods andVLIW (Very Long Instruction Word) methods.

In superscalar methods, specialized circuitry in the processordynamically analyzes which instructions can be executed in parallel andthen has these instructions executed in parallel. These methods have anadvantage in that superscalar processors can be made compatible withserial processing methods. This means that object code that has beengenerated by a compiler for a serial processor can be executed in itsoriginal state by a superscalar processor. A disadvantage of superscalartechniques is that specialized hardware needs to be provided in theprocessor to dynamically analyze the parallelism of instructions, whichleads to an increase in hardware costs. Another disadvantage is that theprovision of specialized hardware makes it difficult to raise theoperation clock frequency.

In VLIW methods, a plurality of instructions that can be executed inparallel are arranged into an executable code of a fixed length, withthe instructions in the same executable code being executed in parallel.For VLIW methods, an “executable code” is a unit of data that is fetchedfrom memory in one cycle or is decoded and executed in one cycle.

For VLIW methods, there is no need during execution for the processor toanalyze which instructions can be executed in parallel. This means thatlittle hardware is required, and that raising the operation clockfrequency is easy. However, the use of fixed-length instructions leadsto the problems described below.

In VLIW executable codes, there is a significant variation in the numberof bits required to define different kinds of instructions. As examples,instructions that deal with a long constant, such as an address or animmediate, require a large number of bits, while instructions thatperform calculations using registers may be defined using fewer bits. Asstated above, VLIW deal with executable codes of a fixed length, so thatNOP codes need to be inserted into instructions that only require a lownumber of bits. This increases code size.

To solve this problem, a technique that fetches a fixed amount of codefrom memory in each cycle but decodes and executes a variable amount ofcode has been proposed in recent years. Hereafter, this technique willbe referred to as the “fixed-supply/variable-execution method”.

FIG. 1A shows the instruction supply unit used in thefixed-supply/variable-execution method. Since there is variation in thenumber of bits needed to define different instructions, two differentformats are used. Instructions that require a large number of bits use afirst format composed of two units, units 1 and 2, while instructionsthat only require few bits use a second format composed of one unit,unit3. Here, instructions that have a length of one unit are called“short instructions”, while instructions that have a length of two unitsare called “long instructions”.

While there are both short and long instructions, instructions aresupplied three units at a time, with no attention being paid to thedifferences in types.

FIG. 1B shows the units (hereafter called “packets”) for fetchinginstructions from memory in each cycle in thisfixed-supply/variable-execution method. FIG. 1C, meanwhile, shows theminimum units (hereafter called “execution units”) for decoding andexecution by this processor.

During execution, all instructions in an area in FIG. 1B demarcated byparallel processing boundaries are executed in parallel in one cycle.This means that in each cycle instructions are executed in parallel asfar as the instruction that is set the next parallel processing boundaryshown in FIG. 1B using shading. Instructions that have been supplied butare not executed are accumulated in an instruction buffer and areexecuted in a following cycle.

In FIG. 1B, the parallel processing boundary is set at unit6, so thatall units from unit1 to unit6 are set as one execution unit. Of theseunits, unit1˜unit2, unit3˜unit4, and unit5˜unit6 each compose a longinstruction, so that these three long instructions are executed inparallel.

The next parallel processing boundary in FIG. 1B is set at unit11, sothat all units from unit7 to unit11 are executed in one execution unit.Of these units, unit7˜unit8 compose a long instruction, unit9 composes ashort instruction, and unit10˜unit11 compose a long instruction. Thesethree instructions are executed in parallel.

In this method, instructions are supplied using a fixed-length packet,and a suitable number of units is issued in each cycle based oninformation that is found through static analysis. Using this method,there is absolutely no need to insert the no operation instructions (NOPcodes) that are required in conventional VLIW methods with fixed lengthinstructions. As a result, code size can be reduced.

The following describes the hardware construction of a processor forthis fixed-supply/variable-execution method.

FIG. 2 is a block diagram showing the construction of the instructionregister and periphery in a processor that is capable of executing threeinstructions in parallel. The broken lines in FIG. 2 show the controlflows. The unit queue in FIG. 2 is a sequence of units. These units aretransferred to the instruction registers in the order in which they weresupplied from the instruction memory (or similar).

In this construction, the instruction register A 52a and the instructionregister B 52b form one pair, as do the instruction register C 52c˜theinstruction register D 52d and the instruction register E 52e˜theinstruction register F 52f. Instructions are always arranged so as tostart from one of the instruction register A 52a, the instructionregister C 52c, and the instruction register E 52e. Only when aninstruction is formed of two linked units is part of the instructionsent to the other instruction register in a pair. As a result, when theunit transferred to the instruction register 52a is a completeinstruction in itself, no unit is transferred to the instructionregister B 52b.

The main characteristic of the above processor is that parallelprocessing can be performed for any combination of short and longinstructions.

When three long instructions are to be executed in parallel, the threelong instructions will be composed of three pairs unit1˜unit2,unit3˜unit4, and unit5˜unit6 in the unit queue 50. The present processorstores the first long instruction in the pair of the instructionregister A 52a˜instruction register B 52b, the second long instructionin the pair of the instruction register C 52c˜instruction register D52d, and the third long instruction in the pair of the instructionregister E 52e˜instruction register F 52f. After being stored in thisway, the three long instructions are executed by the first instructiondecoder 53a˜third instruction decoder 53c.

When the three instructions to be executed in parallel are the longinstruction composed of unit1˜unit2, the short instruction composed ofunit3, and the long instruction composed of unit5˜unit6, the presentprocessor stores the first instruction in the pair of the instructionregister A 52a˜instruction register B 52b, the second instruction in theinstruction register C 52c, and the third instruction in the pair of theinstruction register E 52e˜instruction register F 52f. Nothing is storedin the instruction register D 52d. After being stored in this way, thethree instructions are executed by the first instruction decoder53a˜third instruction decoder 53c.

When unit1˜unit2 and unit3˜unit4 in the unit queue 50 compose two longinstructions and unit5 composes one short instruction, the presentprocessor stores the first instruction in the pair of the instructionregister A 52a˜instruction register B 52b, the second instruction in thepair of the instruction register C 52c˜instruction register D 52d, andthe third instruction in the instruction register E 52e. Nothing isstored in the instruction register F 52f. After being stored in thisway, the three instructions are executed by the first instructiondecoder 53a˜third instruction decoder 53c.

As should be clear from the above description, there is no universaldefinition of the instruction register to which each unit is the unitqueue is to be transferred. There is also no universal definition of theunits in the unit queue that are to be transferred to each instructionregister. For this reason, the selectors 51a˜51d are provided todetermine the destinations of units transferred from the unit queue.These selectors 51a˜51d are controlled in the following way. First,control is performed to determine the output destination of selectors51a and 51b, and the units to be transferred to the instructionregisters C 52c˜instruction register D 52d are determined. Once theunits to be transferred have been determined, information regarding thelength of the instruction in the unit transferred to the instructionregister C 52c is examined and control is performed as shown by thebroken lines in FIG. 2 to determine the output destinations of theselectors 51c and 51d.

While the above processor can decode instructions regardless of thecombination of short and long instructions and regardless of how theopcodes are located in the units, the bit width of the input ports forthe first-third instruction decoders 53a˜53c is two units, whichincreases the overall hardware scale. Putting this another way, theprocessor is deficient in having an overly large hardware scale. Theprocessor includes selectors that switch the output destinations of theinstructions after referring to information regarding the lengths of theinstructions in the units that are transferred to the instructionregisters, so that the hardware construction becomes increasinglycomplex as the number of instruction to be executed in parallelincreases.

One conventional method for reducing hardware scale is that describedfor the GMICRO/400 processor in the article The Approach to MultipleInstruction Execution in the GMICRO/400 Processor given in PROCEEDINGS,The Eighth TRON Project Symposium (International) 1991.

FIG. 3A is a block diagram showing the construction of the instructionregister and periphery for the instruction issuing control method usedby the GMICRO/400 processor. In FIG. 3A, the broken lines show thecontrol flows. The constant operands 54a˜54b are indicated by the outputof the first instruction decoder 53i˜the third instruction decoder 53k.Each instruction decoder decodes an inputted instruction and outputssignals to the execution control unit to control the execution of theinstruction, as well as outputting the constant operands indicated inthe instruction.

The instruction issuing control method of the GMICRO/400 processordecodes the combination unit1˜unit2, and unit2 and unit3 separately.After the decoding of the first instruction decoder 53i has clarifiedwhether the first instruction is a one-unit instruction or a two-unitinstruction, the selector 51g is controlled so that the decoding resultof only one of the second instruction decoder 53j and the thirdinstruction decoder 53k is selected and used. As a result, the processorcan execute both instructions in either the short instruction-shortinstruction combination or the short instruction-long instructioncombination of FIG. 3B in parallel.

As shown in FIG. 3A, the GMICRO/400 decreases the number of instructionsthat can be executed in parallel from three to two, so that only twodecoders are provided². The second instruction decoder 53j and the thirdinstruction decoder 53k also have input ports that are only one unitwide, so that hardware reductions can be made.

²Transistor's note: Apparent mistake in the original Japanese. Threedecoders are present.

The above processor has a different problem, however, in that despitebeing equipped with three decoders, only two instructions can beexecuted in parallel, representing a marked decrease in parallelism whencompared with the hardware shown in FIG. 2. The second of the twoinstructions that can be processed in parallel is also limited to oneunit, giving rise to the further restriction of short instruction-longinstruction combinations also be prohibited.

SUMMARY OF THE INVENTION

It is a primary object of the present invention to provide a processorthat does not need a large hardware scale and can execute a maximum of sinstructions in parallel despite being equipped with only s decoders.The invention also aims to provide an instruction conversion apparatus,a recording medium storing parallel execution codes to which a pluralityof instructions have been assigned, and a computer-readable recordingmedium storing an instruction conversion program that generates suchparallel execution codes.

This primary object can be achieved by an instruction conversionapparatus that includes an assigning unit for successively assigninginstructions in an instruction sequence to parallel execution codes anda control unit for controlling the assigning unit so that a combinationof a plurality of instructions that have already been assigned to aparallel execution code and an instruction that the assigning unit isabout to assign to the parallel execution code satisfy predeterminedlimitations of a target processor.

With the above instruction conversion apparatus, a plurality ofinstructions are assigned to a parallel execution code in keeping withthe predetermined limitations of the processor. Accordingly, the bitwidth and circuit constructions of the plurality of decoders that areincluding in the decoding unit of the processor can be simplified.

Here, when instructions to be assigned to a parallel execution codeinclude a long instruction whose word length is equal to at least twobut no more than k unit fields, the assigning unit may assign one of anopcode and an operand of the long instruction to a u^(th) (where u isany integer such that 1≦u≦s) unit field between the 1^(st) unit fieldand the s^(th) unit field, and only an operand of the long instructionto unit fields from a (u+1)^(th) unit field to a (u+k−1)^(th) unitfield.

With the stated construction, when up to s instructions are arrangedinto a parallel execution code, the s or fewer opcodes included in the sor fewer instructions are arranged without fail into the start of theunit fields between the 1^(st) unit field and the s^(th) unit field.Since the s opcodes are arranged at the start of unit fields, parallelexecution of all of the opcodes included in an executable code will bepossible with only s decoders.

Here, the instruction conversion apparatus may also include a groupingunit for forming an instruction group of a plurality of instructionsthat do not exhibit a dependency relation (hereafter “data dependencyrelation”), a data dependency relation being a relation between aninstruction defining a resource and an instruction referring to the sameresource; and a first detecting unit for detecting, when a 1^(st) to ans^(th) unit field in a parallel execution code have been assigned atleast one instruction by the assigning means and an instruction(hereafter “short instruction”) with a shorter word length than a longinstruction is left in the instruction group, a long instructionassigned to unit fields between the 1^(st) unit field and the s^(th)unit field, wherein the control unit may include a first control subunitfor controlling the assigning unit to rearrange instructions that havealready been assigned to the parallel execution code so that thedetected long instruction is assigned to unit fields between the s^(th)unit field and the (s+k−1)^(th) unit field and the short instructionremaining in the instruction group is assigned to a unit field betweenthe 1^(st) unit field and the (s−1)^(th) unit field.

With the stated construction, all of the opcodes included in a parallelexecution code can be executed in parallel even when the 1^(st) tos^(th) unit fields in a parallel execution code are occupied by aplurality of instructions and a short instruction is left.

Here, the instruction group may include instructions that exhibit ananti-dependence and instructions that exhibit an output dependence, ananti-dependence being a relation between an instruction that refers to aresource and an instruction that thereafter defines the resource, and anoutput dependence being a relation between an instruction that defines aresource and another instruction that defines the resource, the controlunit may include a search unit for searching for a combination pattern,composed of a plurality of instructions in the instruction group, thatis unaffected by an anti-dependence and an output dependence, and thecontrol unit may control the assigning unit to rearrange the pluralityof instructions in accordance with the combination pattern found by thesearch unit, to assign the long instruction found by the detecting meansto unit fields from the s^(th) unit field to the (s+k−1)^(th) unitfield, and to assign a short instruction left in the instruction groupto a unit field between the 1^(st) unit field and the (s−1)^(th) unitfield.

When there is an instruction in an anti- or an output dependence withone of the instructions in the instruction group, such instruction maybe assigned to a parallel execution code to increase the number ofinstructions executed in parallel. When doing so, the assigning ofinstructions in an order that affects the dependency is preventedbeforehand.

Here, the instruction conversion apparatus may also include: an addressresolving unit for assigning a real address to a parallel executioncode; and a second detecting means for detecting, when a real addresshas been assigned to a parallel execution code, an instruction includingthe real address than cannot be expressed by an original word length ofthe instruction, a flag setting unit setting the boundary flag at a unitfield located one of before and after unit fields to which theinstruction detected by the second detecting unit has been assigned.

With the stated construction, processing following the assignment ofinstructions to parallel execution codes converts the parallel executioncodes into object codes and assign real addresses. When the word lengthof any of the instructions needs to be increased, appropriate changesare made to the parallel execution codes in the converted object codestate. As a result, there is no need to reassign the plurality ofinstructions to the parallel execution codes or to reconvert suchparallel execution codes to object codes. Accordingly, such processingcan be performed without reducing the efficiency of program development.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, advantages and features of the invention willbecome apparent from the following description thereof taken inconjunction with the accompanying drawings which illustrate a specificembodiment of the invention. In the drawings:

FIG. 1A shows a format composed of two units, unit1˜unit2, forinstructions that require a large number of bits, and a format composedof one unit, unit3, for other instructions;

FIG. 1B shows the unit (packet) of data that is fetched from memory inone cycle in the fixed-supply/variable-execution method;

FIG. 1C is a block diagram showing the smallest units that are decodedand executed by a processor;

FIG. 2 is a block diagram showing the construction of the instructionregister and periphery in a processor that can execute threeinstructions in parallel;

FIG. 3A is a block diagram showing the construction of the instructionregister and periphery when the instruction issuing control method usedby the GMICRO/400 is used;

FIG. 3B shows the combinations of instructions that can be executed inparallel by the hardware shown in FIG. 3A;

FIG. 4 is a block diagram showing the hardware construction of theprocessor of the first embodiment,

FIG. 5A shows the amounts of data used when the instruction fetch unit21 fetches instructions into the instruction buffer 22;

FIG. 5B shows the amounts of data used when the instruction buffer 22outputs units to the instruction register 23;

FIG. 5C shows how the instruction register 23 issues units to thedecoding unit 30;

FIGS. 6A-6F show the instruction formats used by the present processor;

FIG. 7 shows the combinations of instructions that can be decoded by thedecoding unit 30;

FIG. 8 shows the detailed construction of the instruction buffer 22;

FIGS. 9A-9F show supplying of packets from the instruction fetch unit 21to the instruction buffer 22 and the outputting of units to theinstruction register 23;

FIGS. 10A-10E show the supplying of packets from the instruction fetchunit 21 to the instruction buffer 22 and the outputting of units to theinstruction register 23, though some of the units are not issued by theinstruction register 23;

FIG. 11 is a block diagram showing the construction of the periphery ofthe instruction register 23;

FIG. 12 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33˜third instruction decoder35 when the instruction pattern A shown in FIG. 7 is outputted to thefirst instruction decoder 33˜third instruction decoder 35;

FIG. 13 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33˜third instruction decoder35 when the instruction pattern B shown in FIG. 7 is outputted to thefirst instruction decoder 33-third instruction decoder 35.

FIG. 14 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33˜third instruction decoder35 when the instruction pattern C shown in FIG. 7 is outputted to thefirst instruction decoder 33-third instruction decoder 35;

FIG. 15 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33˜third instruction decoder35 when the instruction pattern D shown in FIG. 7 is outputted to thefirst instruction decoder 33˜third instruction decoder 35;

FIG. 16 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33-third instruction decoder35 when the instruction pattern E shown in FIG. 7 is outputted to thefirst instruction decoder 33˜third instruction decoder 35;

FIG. 17 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33-third instruction decoder35 when the instruction pattern F shown in FIG. 7 is outputted to thefirst instruction decoder 33˜third instruction decoder 35;

FIG. 18 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33-third instruction decoder35 when the instruction pattern G shown in FIG. 7 is outputted to thefirst instruction decoder 33-third instruction decoder 35;

FIG. 19 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33-third instruction decoder35 when the instruction pattern H shown in FIG. 7 is outputted to thefirst instruction decoder 33˜third instruction decoder 35;

FIG. 20 shows the format of parallel execution codes;

FIG. 21 is a block diagram showing the construction of the instructionconversion apparatus of the present embodiment and the related data;

FIGS. 22A˜22F show examples of assembler codes and a dependency graph;

FIG. 23A is a flowchart showing the processing of the instructionrearranging unit 121;

FIG. 23B is a flowchart showing the processing that judges whetherarrangement is possible;

FIG. 24 is a flowchart showing the processing of the address resolvingunit 123 provided inside the linking unit 114;

FIG. 25 is a flowchart showing an example of a process that handles a32-bit constant;

FIG. 26A and FIG. 26B respectively show an example of the executablecodes to a program that has the present processor execute the processingshown in FIG. 25 and an execution image;

FIG. 27A shows example assembler codes;

FIG. 27B shows an example dependency graph that corresponds to FIG. 27A;

FIG. 27C shows the content of the parallel execution codes;

FIGS. 27D, E show the codes after the addition of parallel executionboundaries;

FIG. 28A shows example assembler codes;

FIG. 28B shows an example dependency graph that corresponds to FIG. 28A;

FIG. 28C shows the content of the parallel execution codes;

FIG. 28D shows the codes after the addition of parallel executionboundaries;

FIGS. 29A˜29B respectively show an example of the executable codes in aprogram that has a conventional VLIW processor with a fixed instructionlength of 32 bits execute the processing shown in FIG. 25 and anexecution image;

FIGS. 30A˜30B respectively show an example of the executable codes in aprogram that has a conventional processor that executes 32-bitinstructions including parallel execution boundary information executethe processing shown in FIG. 25 and an execution image; and

FIGS. 31A-31B respectively show an example of the executable codes in aprogram that has a conventional processor that executes 40-bitinstruction including parallel execution boundary information executethe processing shown in FIG. 25 and an execution image.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following describes a processor that is an embodiment of the presentinvention, with reference to the accompanying drawings.

Hardware Construction of the Processor

FIG. 4 is a block diagram showing the hardware construction of theprocessor of the first embodiment.

This processor executes a maximum of three instructions in parallel inone cycle. The hardware of this processor can be roughly divided into aninstruction supplying/issuing unit 20, a decoding unit 30, and anexecuting unit 40.

The instruction supplying/issuing unit 20 supplies sets of instructionsthat it receives from an external memory (not illustrated) to thedecoding unit 30. This instruction supplying/issuing unit 20 includes aninstruction fetch unit 21, an instruction buffer 22, and an instructionregister 23.

The instruction fetch unit 21 fetches instruction units (hereafter“units”) from the external memory (not illustrated) via a 32-bit 1A bus(instruction address) and a 64-bit ID (instruction data) bus and storesthe fetched units in an internal instruction cache. The instructionfetch unit 21 also supplies addresses outputted by the PC unit 42 to theinstruction buffer 22.

FIG. 5A shows the amounts of data used when the instruction fetch unit21 fetches instructions into the instruction buffer 22. As shown in FIG.5A, fetching is performed in 64-bit length blocks (hereafter called“packets”) including three units. The total length of three units is 63bits, so that one bit in the 64 bits is left unused.

The instruction buffer 22 has two 64-bit buffers in a two-stageconstruction, and accumulates the packets supplied by the instructionfetch unit 21. The instruction buffer 22 outputs four of the unitsstored in the two accumulated packets to the instruction register 23.FIG. 5B shows the amounts of data used when the instruction buffer 22outputs units to the instruction register 23. In FIG. 5B, the top levelshows that the instruction buffer 22 outputs the first four units unit1,unit2, unit3, and unit4 to the instruction register 23 out of the unitsunit1˜unit6 that were supplied to three-unit packets in FIG. 5A. Thesecond level shows that the instruction buffer 22 outputs the next fourunits unit5, unit6, unit7, and unit8 to the instruction register 23 outof the units unit4˜unit9 that were supplied in three-unit packets inFIG. 5A.

The instruction register 23 is composed of four 21-bit registers andstored the four units that are transferred from the instruction buffer22. The instruction register 23 issues up to four of these units to thedecoding unit 30. FIG. 5C shows how the instruction register 23 issuesunits to the decoding unit 30. The top level in FIG. 5C shows that theinstruction register 23 first issues unit1 and unit2 to the decodingunit 30, while the second level shows that the instruction register 23next issues unit3-unit6 to the decoding unit 30. The third level showsthat the instruction register 23 then only issues unit7, the fourthlevel shows that the instruction register 23 issues unit8˜unit10 and thefifth level shows that the instruction register 23 issues unit11˜unit12. As shown in FIG. 5C, the instruction register 23 issuesbetween one and four units, out of the four units transferred from theinstruction buffer 22, to the decoding unit 30.

The shaded parts of FIGS. 5A and 5B show the boundaries (parallelexecution boundaries) when units are outputted from the instructionregister 23 to the decoding unit 30. As can be seen from these parallelexecution boundaries, the supplying of units from the instruction fetchunit 21 to the instruction buffer 22 and the transferring of units fromthe instruction buffer 22 to the instruction register 23 are bothperformed with no relation to the output units used for outputting fromthe instruction register 23 to the decoding unit 30.

The instruction issuing control unit 31 refers to the parallel executionboundary information and format information in the units stored in thefour registers of the instruction register 23 and performs control sothat two units are treated as one instruction when necessary. Theinstruction issuing control unit 31 also performs control so that theissuing of units is not performed beyond a parallel execution boundary.

The following first explains the construction of the instructions storedin the instruction register 23 and the storage position of the parallelexecution boundary information f10 and the format information f11.

FIGS. 6A˜6F show the instruction formats used by the present processor.Each instruction of the present processor is composed of a minimum of 21bits, with there being both one-unit instructions that are 21-bitinstructions and two-unit instructions that are 42-bit instructions. Thelength of each kind of instruction is decided by the format informationf11 that is one bit long. When the format information f11 is “0”, oneunit forms an instruction by itself, while when the format informationf11 is “1”, that unit and the following unit together form one 42-bitinstruction.

The MSB (most significant bit) in each instruction is the parallelexecution boundary information f10. This parallel execution boundaryinformation f10 shows whether a parallel execution boundary is presentbetween the present instruction and the following instruction. When theparallel execution boundary information f10 is “1”, a parallel executionboundary is present between this instruction and the followinginstruction, while when the parallel execution boundary information f10is “0”, no parallel execution boundary is present between thisinstruction and the following instruction. If the first to fourth unitsissued by the instruction register 23 are divided using the parallelexecution boundary information f10 and the format information f11, thesefour units can be decoded as instructions in one of the patterns A-Hshown in FIG. 7. However, due to the hardware construction of thedecoding unit 30, the instructions of the patterns 1 and J shown in FIG.7 cannot be executed in parallel. This means that if a 21-bitinstruction is called a short instruction and a 42-bit instruction along instruction, the following combinations of instructions cannot beexecuted.

short-long-long long-short-short long-short-long long-long-shortlong-long-long

Also note that the instructions in the patterns A˜H shown in FIG. 7 donot need to be simultaneously executed. When instructions cannot betimely supplied parallel execution codes may be divided into two or moreparts that are separately executed. When doing so, theparallel-executable instructions are processed so that instructions thatare closer to the MSB are executed in a first cycle and instructionsthat are closer to the LSB (least significant bit) are executed in afollowing cycle.

The operation of this instruction issuing control unit 31 is shown inmore detail in other drawings.

The instruction decoder 32 includes a first instruction decoder 33, asecond instruction decoder 34, and a third instruction decoder 35 whicheach have an input port that is 21 bits wide. These decodersfundamentally decode one 21-bit instruction in one cycle, and sendcontrol signals to the executing unit 40. These decoders also transferthe constant operands that are located in each instruction to the databus 48 of the executing unit 40.

Aside from the format information f11 and the parallel executionboundary information f10, FIGS. 6A-6F also show the operation that areindicated by various kinds of instructions. FIGS. 6A-6C show the formatsof 21-bit instructions, while FIGS. 6D-6F show the formats of 42-bitinstructions.

In these formats, transfer instructions and arithmetic instructions thathandle long constants such as 32-bit constants, and branch instructionsthat indicate a large displacement are defined as 42-bit instructions.Most other kinds of instructions are defined as 21-bit instructions.

These instructions are such that 19 bits may be used in a 21-bitinstruction and 40 bits may be used in a 42-bit instruction. In detail,the format in FIG. 6A includes an opcode “Op1” that shows the type ofoperation, an “Rs” field that shows the register number of the registerused as the source operand, and an “R” field that shows the registernumber of the register used as the destination operand.

The format in FIG. 6B includes an opcode “Op1” that shows the type ofoperation, an “imm5” field that shows a 5-bit immediate used as thesource operand, and an “Rd” field that shows the register number of theregister used as the destination operand.

The format in FIG. 6C includes an opcode “Op2” that shows the type ofoperation, and a “disp13” field that shows a 13-bit immediate used asthe source operand.

The “imm5” field indicates a 5-bit constant that is used as an operand.The “disp13” field indicates a 13-bit displacement.

Each of the instructions shown in FIGS. 6A-6C may be inputted into oneof the first instruction decoder 33˜third instruction decoder 35. Theopcode and any register numbers in an instruction are decoded by thefirst instruction decoder 33˜third instruction decoder 35 which sendcontrol signals showing the decoding results to the executing unit 40.On the other hand, immediates and displacements are outputted by thefirst instruction decoder 33˜third instruction decoder 35 to the thirdinstruction decoder 35 in their original form.

The following explains the formats of 42-bit instructions.

The format in FIG. 6D includes an opcode “Op1” that shows the type ofoperation, a “disp21” field that shows a 21-bit displacement used as thesource operand, and an “Rd” field that shows the register number of theregister used as the destination operand.

The format in FIG. 6E includes an opcode “Op3” that shows the type ofoperation, an “imm32” field that shows a 32-bit immediate used as thesource operand, and an “Rd” field that shows the register number of theregister used as the destination operand.

The format in FIG. 6F includes an opcode “Op1” that shows the type ofoperation, and a “disp31” field that shows a 31-bit displacement used asthe source operand.

Since each of the first instruction decoder 33 to third instructiondecoder 35 only have a 21-bit input port, none of these decoders is ableto receive an input of an entire 42-bit instruction. Accordingly, thefirst instruction decoder 33˜third instruction decoder 35 only receivesas input of a part of a 42-bit instruction shown in FIGS. 6D to 6F asthe 20^(th) to 39^(th) bits, which is to say, only the first unit. Thesecond unit in such an instruction is not inputted into any of the firstinstruction decoder 33˜third instruction decoder 35 and is insteadinputted directly into the executing unit 40 without passing the firstinstruction decoder 33˜third instruction decoder 35.

The second unit may skip the first instruction decoder 33˜third unitdecoder 35 for the following reason. As can be seen from the instructionformats shown in FIGS. 6E and 6F, the second of the two units that forma 42-bit instruction only includes part of a constant operand. Thismeans that the second unit is an instruction format that does notinclude an opcode, so that the second unit does not need to be inputtedinto the first instruction decoder 33˜third instruction decoder 35.Accordingly, such input can be skipped.

The constant operand of a 42-bit instruction is therefore composed bylinking a constant in the unit that is outputted by an instructiondecoder with a constant that skips the first instruction decoder33˜third instruction decoder 35 and is directly transferred in theexecuting unit 40.

The executing unit 40 is a circuit for executing a maximum of threeunits in parallel, based on the control signals received from thedecoding unit 30. This executing unit 40 includes an execution controlunit 41, a PC unit 42, a register file 43, a first calculating unit 44,a second calculating unit 45, a third calculating unit 46, an operandaccess unit 47, and data buses 48 and 49.

The execution of instructions is such that units (hereafter “executionunits”) between parallel execution boundaries are executed in parallelin one cycle. This means that in each cycle, instructions are executedas far as the first instruction whose parallel execution boundaryinformation f10 is “1”. Instructions that have been supplied but whichare not executed are accumulated in the instruction buffer and areexecuted in a later cycle.

The execution control unit 41 is a general name for the controlcircuitry and wiring that controls the components 42˜49 in the executingunit 40 according to the decoding results of the decoding unit 30. Thisexecution control unit 41 includes circuits for timing control,execution permission/prohibition control status management, andinterrupt control.

The PC (program counter) unit 42 outputs an address in the externalmemory at which a next instruction to be decoded and executed is locatedto the instruction fetch unit 21 of the instruction supplying/issuingunit 20.

The register file 43 is composed of thirty-two 32-bit registers numberedregister R0˜R31. The values stored in these registers are transferred tothe first calculating unit 44, the second calculating unit 45, and thethird calculating unit 46 via the data bus 48, based on the decodingresults of the first instruction decoder 33, the second instructiondecoder 34, and the third instruction decoder 35. The calculating unitsperform calculations on the register data or simply allow the values topass, before outputting values to the register file 43 or the operandaccess unit 47 via the data bus 49.

The first calculating unit 44, the second calculating unit 45, and thethird calculating unit 46 each include an ALU (arithmetic logic unit)and multiplier that perform calculations on two pieces of 32-bit data,as well as a barrel shifter that performs shift operations. Thesecalculating units execute calculations under the control of theexecution control unit 41.

The operand access unit 47 transfers operands between the register file43 and the external memory. When, for example, an instruction has “ld”(load) as its opcode, one word (32 bits) of data located in the externalmemory is loaded into an indicated register in the register file 43 viathe operand access unit 47. When an instruction has “st” (store) as itsopcode, the stored value of an indicated register in the register file43 is stored into the register file 43.

As shown in FIG. 4, the PC unit 42, the register file 43, the firstcalculating unit 44, the second calculating unit 45, the thirdcalculating unit 46, and the operand access unit 47 are all connected tothe data bus 48 (L1 bus, R1 bus, L2 bus, R2 bus, L3 bus, and R3 bus) andthe data bus 49 (D1 bus, D2 bus, and D3 bus). Note that the L1 bus andR1 bus are respectively connected to the two input ports of the firstcalculating unit 44, the L2 bus and R2 bus are respectively connected tothe two input ports of the second calculating unit 45, and the L3 busand R3 bus are respectively connected to the two input ports of thethird calculating unit 46. The D1 bus, D2 bus, and D3 bus arerespectively connected to the outputs of the first calculating unit 44,the second calculating unit 45, and the third calculating unit 46.

With this architecture, instructions are supplied in packets of a fixedlength, and a suitable number of units for the degree of parallelism isissued based on statically obtained information. This method does notrequire any no operation (NOP) instructions that are issued inconventional VLIW methods with fixed-length instructions, so that theoverall code size is reduced.

According to the value of the format information f11, two units may beexecuted as one instruction or one unit may be executed as oneinstruction. As a result, a long instruction format is only used forcertain instructions that require a large number of bits, with otherinstructions being defined using a short instruction format. Thisachieves a further reduction in code size.

Detailed Construction of the Instruction Buffer

The following describes the instruction buffer 22 in detail. FIG. 8shows the detailed construction of the instruction buffer 22.

The instruction buffer 22 is composed of two 63-bit buffers, theinstruction buffer A221 and the instruction buffer B222, that each storethree units. The instruction buffer A221 is composed of three 21-bitbuffers A0, A1, and A2 that each store one unit. In the same way, theinstruction buffer B222 is composed of three 21-bit buffers B0, B1, andB2 that each store one unit.

The instruction buffer 22 is supplied with 64-bit packets by theinstruction fetch unit 21. However, the MSB of the packet is not used asinformation. When a packet is received, the 63 valid bits in the packetare stored into one of the instruction buffer A221 and the instructionbuffer B222 with no crossover between the two. The units stored in theinstruction buffer 22 are stored in the order in which they weresupplied, with the instruction buffer control unit 223 managing thestatus of the instruction buffer 22, such as this supplying order andwhether either instruction buffer stores valid data.

The instruction buffer control unit 223 assigns a predetermined transferorder to the six units stored in the instruction buffer A221 and theinstruction buffer B222, and controls the selectors 224a, 224b, 224c,and 224d so as to transfer units to the instruction registers A231˜D234in accordance with this order. This transfer order is determined basedon the order in which packets are transferred from the instruction fetchunit 21 to the instruction buffer 22 and the positions of the variousunits within these packets.

In detail, the packets stored in the instruction buffers A221 and B222are given a transfer order in accordance with the order in which theywere supplied from the instruction supplying/issuing unit 20.

The three units in each packet are given a transfer order that treatsthe units as a first unit, a second unit, and a third unit, startingfrom the unit closest to the MSB. In order starting from the first unitto be received, units are transferred from the instruction buffers A221and B222 to the instruction registers A231˜D234. By assigning thistransfer order to units, a waiting queue is formed using the six unitsin the instruction buffers A221 and B222. This waiting queue ishereafter called the “unit queue”.

In this unit queue composed of six units, the first four units aretransferred to the instruction registers A231-D234 as shown in FIG. 5B.After this transfer, the four units may be issued from the instructionregisters A231-D234 to the first instruction decoder 33˜the thirdinstruction decoder 35, as shown in FIG. 5C. Here, up to four units maybe issued, so that there are cases when units that have not been issuedremain in the instruction registers A231-D234. In such cases, theinstruction buffer control unit 223 invalidates the units in theinstruction registers A231-D234 that have been issued to the firstinstruction decoder 33˜third instruction decoder 35 and validates theremaining units. The validated units are then moved upward in the unitqueue.

When a branch occurs, if the branch destination is a unit that is storedin the unit queue, the branch destination unit and following units inthe unit queue are validated. Units positioned before the branchdestination unit in the unit queue are invalidated.

This invalidating and moving up of units in the unit queue is performedbased on information showing which units in the instruction register 23were not issued to the first instruction decoder 33˜third instructiondecoder 35 and on information showing which units in the instructionbuffers A221 and B222 should be validated. Of these, the formerinformation is received from the instruction fetch unit 21, while thelatter information is received as feedback from the instruction issuingcontrol unit 31 of the decoding unit 30.

The following explains the control of buffer states by the instructionbuffer control unit 223 with reference to FIGS. 9A-9F and FIGS. 10-10F.FIGS. 9A-9F show the supplying of packets from the instruction fetchunit 21 to the instruction buffer 22 and the outputting of units to theinstruction register 23. In the same way, FIGS. 10A-10F show thesupplying of packets from the instruction fetch unit 21 to theinstruction buffer 22 and the outputting of units to the instructionregister 23, though in FIGS. 10A-10F some of the units are not issued bythe instruction register 23.

FIG. 9A corresponds to when the instruction buffer 22 is empty and abranch is performed to the second unit in a packet (unit2). In thiscase, the packet (composed of unit1, unit2, and unit3) including thisunit2 is supplied from the instruction fetch unit 21, as shown in FIG.9B, and is stored in the instruction buffer A221.

Since the unit at the start of this packet is invalid, the instructionbuffer control unit 223 performs control as shown in FIG. 9C so that thestate of the instruction buffer 22 is that only the buffers A1 and A2are valid.

If in the next cycle, none of the units transferred from the instructionbuffer 22 to the instruction register 23 is issued and a valid 64-bitpacket composed of unit4, unit5, and unit6 is supplied from theinstruction fetch unit 21, the packet is transferred to the instructionbuffer B222, so that the state of the instruction buffer 22 changes sothat buffers A1, A2, B0, B1, and B2 are all valid.

In the next cycle, there is no space in the instruction buffer 22, asshown in FIG. 9D, so that no supplied packet is received from theinstruction fetch unit 21. Unit2 in buffer a1, unit3 in buffer A2, unit4in buffer B0, and unit5 in buffer B1 are transferred in order to theinstruction register 23.

In this way, the supplying of a packet from the instruction fetch unit21 is only performed when there is a 63-bit space in the instructionbuffer 22. Packets are managed in the order in which they were supplied,so that in each cycle, the four units that were supplied first aretransferred from the instruction buffer 22 to the instruction register23.

When unit2˜unit5 have been issued by the instruction register 23, all ofunit1˜unit5 are invalided as shown in FIG. 9E, resulting in theinstruction buffer A221 becoming empty. As shown in FIG. 9F, thisresults in unit7˜unit9 being supplied to the instruction buffer A221, sothat unit6˜unit9 will be stored in the instruction buffer 221A andinstruction buffer 222B. In FIG. 10A, these units are transferred to theinstruction register 23. Of these units, unit6˜unit8 are issued by theinstruction register 23 to the first instruction decoder 33 and secondinstruction decoder 34, so that only unit9 remains in the instructionregister 23. As a result, all of the units in the instruction buffer222B are invalidated, as shown in FIG. 10B, and all units aside fromunit9 in the instruction buffer 221A are invalidated. This invalidationclears the instruction buffer 222B so that unit10˜unit12 are supplied tothe instruction buffer 222B as shown in FIG. 10C. After this, four unitsstarting from unit9 (unit9˜unit12) are transferred from the instructionbuffer 221A and instruction buffer 222B to the instruction register 23.Of these transferred units, unit9 and unit10 are issued, while unit11and unit12 remain in the instruction register 23. As a result, theinstruction buffer control unit 223 validates only unit11 and unit12 andinvalidates the other units. In the next transfer, three units startingfrom unit11 (unit11˜unit13) are transferred to the instruction register23.

Periphery of the Instruction Register 23 and Operation of theInstruction Issuing Control Unit 31

The following describes the construction of the periphery of theinstruction register 23 and the detailed operation of the instructionissuing control unit 31.

FIG. 11 is a block diagram showing the construction of the periphery ofthe instruction register 23. In FIG. 11, arrows drawn using broken linesindicate control signals.

The instruction register 23 is composed of four 21-bit registers, theinstruction registers A231˜D234. For ease of understanding thisinstruction register 23 is shown as setting a sequence of units suppliedby the instruction buffer 22 as a unit queue.

As shown in FIG. 11, the position in the instruction register 23 towhich a unit is transferred is unequivocally determined by its positionin the unit queue. This means, for example, that the first unit in thequeue will be transferred to the instruction register A231 and thesecond unit will be transferred to the instruction register B232.

The first instruction decoder 33˜third instruction decoder 35 eachreceive an input of a 21-bit unit, decode it, and output control signalsrelating to the operation of the instruction composed by this unit tothe execution control unit 41, as well as outputting any constantoperands located in the unit.

The first instruction decoder 33˜third instruction decoder 35 alsoreceive an input of a 1-bit no-operation flag as a control signal. Whenthis flag is set at “1” for a decoder, the decoder outputs a nooperation instruction. This means that by setting the no-operation flag,the decoder of an instruction by an instruction decoder can beinvalidated.

The instruction issuing control unit 31 refers to the parallel executionboundary information f10 and the format information f11 of the unitsstored in the instruction register A231 and the instruction registerB232, and judges which is the final unit that should be outputted fromthe instruction register 23 in this cycle. Based on this information,the instruction issuing control unit 31 outputs control signals(no-operation instruction flags) that show whether the decoding by thesecond instruction decoder 34 and third instruction decoder 35 should beinvalidated. The instruction issuing control unit 31 then transmitsinformation showing how many units were not issued and so remain in theinstruction register 23 to the instruction buffer control unit 223 inthe instruction buffer 22.

As can be seen from FIG. 11, the units that can be decoded asinstructions are only the units stored in the instruction register A231,the instruction register B232, and the instruction register C233. Theinformation in these units is examined, and decoding is invalidated forunits that correspond to the second unit in a 42-bit instruction andunits that are not issued. A unit that corresponds to the second unit ina 42-bit instruction is directly outputted as part of the constantoperand of the instruction that is composed by the preceding unit.

In order to output these control signals, the instruction issuingcontrol unit 31 is internally equipped with the OR circuit 351 and theOR circuit 352, as shown in FIG. 11.

The OR circuit 351 invalidates the decoding by the second instructiondecoder 34 if the parallel execution boundary information f10 of theunit stored in the instruction register A231 is “1” or if the formatinformation f11 of that unit is “1”.

The OR circuit 352 invalidates the decoding by the third instructiondecoder 35 if the parallel execution boundary information f11 of theunit stored in the instruction register B232 is “1” or if the formatinformation f11 of that unit is “1”.

The following explains the operation of the instruction issuing controlunit 31˜third instruction decoder 35 when decoding the instructionpatterns A˜H shown in FIG. 7, with reference to FIGS. 12˜19.

FIG. 12 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33˜third instruction decoder35 when the instruction pattern A shown in FIG. 7 is outputted to thefirst instruction decoder 33˜third instruction decoder 35. In thisfigure, the parallel execution boundary information f10-formatinformation f11 of the unit (unit`) stored in the instruction registerA231 is “10”. In this case, unit1 forms a 21-bit instruction, so thatdecoding of unit2 and unit3 as instructions is invalidated. This meansthat the instruction issuing control unit 31 sets the no-operation flagsrespectively outputted to the second instruction decoder 34 and thethird instruction decoder 35 at “1”.

FIG. 13 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33˜third instruction decoder35 when the instruction pattern B shown in FIG. 7 is outputted to thefirst instruction decoder 33˜third instruction decoder 35. In thisfigure, the parallel execution boundary information f10-formatinformation f11 of the unit (unit1) stored in the instruction registerA231 is “01”. In this case, unit1 and unit2 stored in the instructionregister B232 together form a 42-bit instruction, so that unit2 is notdecoded as an instruction. This means that the instruction issuingcontrol unit 31 sets the no-operation flags respectively outputted tothe second instruction decoder 34 and the third instruction decoder 35at “1”.

FIG. 14 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33˜third instruction decoder35 when the instruction pattern C shown in FIG. 7 is outputted to thefirst instruction decoder 33˜third instruction decoder 35. In thisfigure, the parallel execution boundary information f10-formatinformation f11 of the unit1 stored in the instruction register A231 is“00”, and the parallel execution boundary information f10-formatinformation f11 of the unit (unit2) stored in the instruction registerB232 is “10”. Since the format information f11 for both units is “0”,only units up to unit2 are issued in this cycle, so that the decoding ofunit3 as an instruction is invalidated. This means that the instructionissuing control unit 31 sets the no-operation flag outputted to thethird instruction decoder 35 at “1”.

FIG. 15 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33˜third instruction decoder35 when the instruction pattern D shown in FIG. 7 is outputted to thefirst instruction decoder 33˜third instruction decoder 35. In thisfigure, the parallel execution boundary information f10-formatinformation f11 of the unit1 stored in the instruction register A231 is“00”, the parallel execution boundary information f10-format informationf11 of the unit2 stored in the instruction register B232 is “01”, andthe parallel execution boundary information f10-format information f11of unit3 stored in the instruction register C233 is “10”. In this case,unit1 stored in the instruction register A231 forms a separate 21-bitinstruction. Meanwhile, unit2 stored in the instruction register B232and unit3 stored in the instruction register C233 together form a 42-bitinstruction, so that the decoding of unit3 as an instruction isinvalidated. This means that the instruction issuing control unit 31sets the no-operation flag outputted to the third instruction decoder 35at “1”.

FIG. 16 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33˜third instruction decoder35 when the instruction pattern E shown in FIG. 7 is outputted to thefirst instruction decoder 33˜third instruction decoder 35. In thisfigure, the parallel execution boundary information f10-formatinformation f11 of unit1 stored in the instruction register A231 is“01”, the parallel execution boundary information f10-format informationf11 of the unit2 stored in the instruction register B232 is “00”, andthe parallel execution boundary information f10-format information f11of unit3 stored in the instruction register C233 is “10”. Since theformat information f11 of unit1 is “1”, unit1 and unit2 in theinstruction register B232 together form a 42-bit instruction. On theother hand, unit3 forms a separate 21-bit instruction and so needs to bedecoded. In this case, the instruction issuing control unit 31 sets onlythe no-operation flag outputted to the second instruction decoder 34 at“1”.

FIG. 17 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33˜third instruction decoder35 when the instruction pattern F shown in FIG. 7 is outputted to thefirst instruction decoder 33˜third instruction decoder 35. In thisfigure, the parallel execution boundary information f10-formatinformation f11 of unit1 stored in the instruction register A231 is“01”, the parallel execution boundary information f10-format informationf11 of the unit2 stored in the instruction register B232 is “00”, theparallel execution boundary information f10-format information f11 ofunit3 stored in the instruction register C233 is “01”, and the parallelexecution boundary information f10-format information f11 of unit4stored in the instruction register D234 is “10”. Since the formatinformation f11 of unit1 is “1”, unit1 and unit2 in the instructionregister B232 together form a 42-bit instruction. The format informationf11 of unit3 is also “01” so that unit3 and unit4 in the instructionregister D234 together form another 42-bit instruction. In this case,the instruction issuing control unit 31 sets only the no-operation flagoutputted to the second instruction decoder 34 at “1”.

FIG. 18 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33˜third instruction decoder35 when the instruction pattern G shown in FIG. 7 is outputted to thefirst instruction decoder 33˜third instruction decoder 35. In thisfigure, the parallel execution boundary information f10-formatinformation f11 of unit1 stored in the instruction register A231 is“00”, the parallel execution boundary information f10-format informationf11 of unit2 stored in the instruction register B232 is “00”, theparallel execution boundary information f10-format information f11 ofunit3 stored in the instruction register C233 is “10”. Since the formatinformation f11 of unit1 is “0”, unit1 stored in the instructionregister A231 forms a separate 21-bit instruction. In the same way, theformat information f11 of unit2 is “0”, so that unit2 stored in theinstruction register B232 forms a separate 21-bit instruction. Also, theformat information f11 of unit3 is “0”, so that unit3 stored in theinstruction register C233 forms a separate 21-bit instruction. Thesethree 21-bit instructions are decoded in parallel by the firstinstruction decoder 33˜third instruction decoder 35.

FIG. 19 shows the control content of the instruction issuing controlunit 31, and the first instruction decoder 33˜third instruction decoder35 when the instruction pattern H shown in FIG. 7 is outputted to thefirst instruction decoder 33˜third instruction decoder 35. In thisfigure, the parallel execution boundary information f10-formatinformation f11 of unit1 stored in the instruction register A231 is“00”, the parallel execution boundary information f10-format informationf11 of unit2 stored in the instruction register B232 is “00”, theparallel execution boundary information f10-format information f11 ofunit3 stored in the instruction register C233 is “01”, and the parallelexecution boundary information f10-format information f11 of unit4stored in the instruction register D234 is “10”. Since the formatinformation f11 of unit1 is “0”, unit1 stored in the instructionregister A231 forms a separate 21-bit instruction. In the same way, theformat information f11 of unit2 is “0”, so that unit2 stored in theinstruction register B232 forms a separate 21-bit instruction. On theother hand, the format information f11 of unit3 is “1”, so that togetherwith unit4 in the instruction register D234, unit3 stored in theinstruction register C233 forms a 42-bit instruction. These two 21-bitinstructions and single 42-bit instruction are decoded in parallel bythe first instruction decoder 33˜third instruction decoder 35.

As described above, the processor of the present embodiment can decodeup to four units in a sequence of units as instructions. This means thatthe patterns A-H shown in FIG. 7 can be issued, meaning that a maximumof four units can be issued at once. However, out of the possiblepatterns composed of four units, the patterns I-J in FIG. 7 have theopcode of the third instruction located in the instruction register234D, so that these instructions cannot be decoded. However, out of thepatterns that include one 42-bit instruction, even the pattern H in FIG.7 can be executed in parallel. This means that even if a processor onlyhas three decoders with 21-bit input ports, three instructions includingone long instruction can still be executed in parallel.

Second Embodiment

In the processor of the first embodiment, instructions are suppliedusing packets that are outputted to the instruction buffer 22 andinstructions are executed using “execution units” that are outputtedfrom the instruction register 23. This second embodiment relates to aninstruction conversion apparatus that generates a sequence of packetsthat are suited to the processor described in the first embodiment. Thisinstruction conversion apparatus generates codes that correspond to the“execution units” described in the first embodiment, and then convertsthese codes into the object codes that correspond to the packets. Thesecodes that correspond to “execution units” are called “parallelexecution codes” in this second embodiment.

FIG. 20 shows the format of parallel execution codes. In FIG. 20, thepossible sizes of the parallel execution codes are 21 bits, 42 bits, 63bits, and 84 bits. Here, 84-bit parallel execution codes can be used toassign the combinations of short and long instructions shown as patternsF, H, I and J in FIG. 7, and 63-bit parallel execution codes can be usedto assign the combination of short and long instructions shown aspatterns D, E, and G in FIG. 7. In the same way, 42-bit parallelexecution codes can be used to assign the combinations of short and longinstructions shown as patterns B and C in FIG. 7, and a 21-bit parallelexecution code can be used to assign one short instruction, as shown bypattern A in FIG. 7. These parallel execution codes include internalfields (unit fields) that are each 21-bits in size. One 21-bit unitdescribed in the first embodiment can be assigned to each of these unitfields. The unit fields in parallel execution code are assigned numbersstarting from the MSB, and so are respectively called the first, thesecond, the third, and the fourth unit fields. Of these unit fields, thefirst to third unit fields can be decoded in order by the firstinstruction decoder 33˜third instruction decoder 35.

When the pattern D in FIG. 7 is assigned, a short instruction isassigned to the first unit field of 63-bit parallel execution code and along instruction is assigned to the second and third unit fields in the63-bit parallel execution code. When the pattern E in FIG. 7 isassigned, a long instruction is assigned to the first and second unitfield of 63-bit parallel execution code and a short instruction isassigned to the third unit field in the 63-bit execution code. When thepattern H in FIG. 7 is assigned, two short instructions are assigned tothe first and second unit fields of 84-bit parallel execution code and along instruction is assigned to the third and fourth unit fields in the84-bit parallel execution code.

Note that when two or more instructions are assigned to a parallelexecution code, there are cases where parallel execution is notpossible. As one example, when the supplying of instructions from theinstruction supplying/issuing unit 20 of the processor in the firstembodiment cannot keep up with the decoding of instructions by thedecoding unit 30, the two or more instructions assigned to the sameparallel execution code will be executed in two or more cycles. Thismeans that only an instruction positioned in the first unit field of theparallel execution code is executed in a first cycle, with theinstruction positioned in the second unit field of the parallelexecution code being executed in the next cycle. Accordingly, theinstruction conversion apparatus has to assign short and longinstructions to unit fields in a way that proper execution will beproperly performed even if the plurality of instructions in a set ofparallel execution code are executed in two or more cycles.

The setting of the lengths of sets of parallel execution code at 21, 42,63, or 84 bits can be made by the instruction conversion apparatussetting the parallel execution boundaries shown in the first embodimentin the parallel execution codes. Parallel execution codes that can haveone of four lengths are serially arranged, and are then divided into63-bit lengths. In this way, the packet sequence shown in the firstembodiment is obtained as a sequence of object codes.

The parallel execution codes generated in this way must satisfy the twoconditions given below.

The first condition is that the plurality of instructions included in aparallel execution code do not violate the restrictions of the processorregarding the available computing resources.

The second condition is that the instructions are assigned within theparallel execution code in accordance with the restrictions on parallelexecution by the processor.

The restrictions regarding the instructions that can be arranged betweenthe parallel execution boundaries are as follows.

-   -   (1) The total number of instructions in a parallel execution        code does not exceed three.    -   (2) The total number of resources in the processor used by the        instructions in a parallel execution code does not exceed three        ALUs, 1 LD/ST unit and a branch unit.    -   (3) The combination of instruction sizes in a parallel execution        code is one of the patterns A˜H shown in FIG. 7.        Construction of the Instruction Conversion Apparatus

The following describes the instruction conversion apparatus of thepresent embodiment, with reference to the drawings. This instructionconversion apparatus is of a format that is conventionally used in theart, which is to say, a recording medium storing executable software fora compiler and linker that have the equivalent functions of aninstruction conversion apparatus. Such recording media are generallydistributed and sold as software packages. A user can purchase andinstall such a software package into a general-purpose computer that canthereafter function as an instruction conversion apparatus simply byprocessing according to the installed software. Since this is the commonmethod for implementing an instruction conversion apparatus, thesoftware for achieving an instruction conversion apparatus is moreimportant than the hardware resources, such as the processor and memory,of the general-purpose computer on which the software is run. Softwarethat has such a complicated processing content is generally composed ofa number of subroutines and work areas, so that each of thesesubroutines and work areas should be considered a separate constructionelement. However, it is common for such subroutines and work areas to bearranged into a library by a conventional operating system, compiler, orlinker, and such components will not be explained here. Accordingly, thefollowing explanation will focus on the functions of the subroutines andwork areas that are required to achieve the functions of an instructionconversion apparatus.

FIG. 21 is a block diagram showing the construction of the instructionconversion apparatus of the present embodiment and the related data.

The construction of the present instruction conversion apparatus can bebroadly divided into the following two groups. The first group generatesobject codes 160 from source codes 150 that are written in a high-levellanguage, comprises the compiler upstream part 110, the assembler codegenerating unit 111, the instruction scheduling unit 112, and the objectcode generating unit 113, and corresponds to a conventional compiler.The second group links a plurality of object codes 160 and generates thefinal executable codes 70, comprises the linking unit 114, andcorresponds to a conventional linker.

Compiler Upstream Part 110

The compiler upstream part 110 reads the source program 150 that isstored as a file. This source program 150 is written in a high-levellanguage, so that the compiler upstream part 110 performs a syntacticand semantic analysis on the source program 150 and generates internalrepresentation codes and an internal representation program composed ofa plurality of internal representation codes. The compiler upstream part110 also optimizes this internal representation program as necessary toreduce the code size and/or execution time of the executable codes thatare finally generated.

Assembler Code Generating Unit 111

The assembler code generating unit 111 generates assembler codes fromthe internal representation codes that have been generated and optimizedby the compiler upstream part 110 and by doing so generates an assemblerprogram composed of a plurality of assembler codes.

The processing of the compiler upstream part 110 and assembler codegenerating unit 111 does not relate to the gist of the present inventionand may be achieved through the processing performed by a conventionalinstruction conversion apparatus. Accordingly, such processing will notbe described in this specification. When assembler codes are generated,it is assumed that it is possible to judge whether the assembler codescorrespond to long instructions or short instructions. Note thatassembler codes that include a displacement as an operand areprovisionally assumed to short instructions at this stage.

Instruction Scheduling Unit 112

The instruction scheduling unit 112 analyzes dependencies betweeninstructions in the assembler codes generated by the assembler codegenerating unit 111, performs instruction scheduling (reordering ofinstructions), and adds parallel execution boundaries, assigningassembler codes that can be executed in parallel to a same parallelexecution code. When doing so, the instruction scheduling unit 112 alsoconsiders the case where instructions assigned to a same parallelexecution code are executed separately in two cycles, and assignsinstruction to unit fields so as to ensure that there will be nobreakdown in the dependencies even if the instructions are executed indifferent cycles. To perform such assigning, the instruction schedulingunit 112 includes a dependency analyzing unit 120, an instructionrearranging unit 121, and a parallel execution boundary appending unit122. To simplify the explanation, the instruction scheduling unit 112 isassumed here to process the assembler codes in basic block units.

The dependency analyzing unit 120 analyzes the dependencies betweeninstructions in a basic block and produces a dependency graph. In thisspecification, there are the following three types of dependenciesbetween instructions:

-   -   data dependence—dependency between an instruction that defines a        resource and an instruction that refers to the same resource;    -   anti-dependence—dependency between an instruction that refers to        a resource and an instruction that defines the same resource;        and    -   output dependence—dependency between an instruction that defines        a resource and another instruction that defines the same        resource.

Rearranging the original order of instructions so that instructions thatexhibit any of the above types of dependencies are interchanged willaffect the meaning of the program. Accordingly, such dependencies needto be maintained when rearranging the instructions.

The dependency analyzing unit 120 refers to the result of its analysis,generates a node for each instruction that is included in a basic block,and generates edges (arrows) joining pairs of instructions that exhibita dependency. As one example, FIG. 22B shows a dependency graph thatcorresponds to the assembler codes shown in FIG. 22A. In FIG. 22A,instruction1 “ld (mem1),R0” and instruction2 “add 1,R0” have a datadependency regarding register R0. In the same way, instruction2 “add 1,R0” and instruction3 “st R0,(mem2)” have a data dependency regardingregister R0.

Instruction3 “st R0,(mem2)” and instruction4 “mov R1,R0” have ananti-dependence regarding register R0.

In the same way, instruction4 “mov R1,R0” and instruction6 “add R3,R0”have a data dependency regarding register R0, instruction5 “mov R2,R3”and instruction6 “add R3,R0” have a data dependency regarding registerR3, and instruction6 “add R3,R0” and instruction7 “st R0,(mem3)” have adata dependency regarding register R0.

Instructions that exhibit a data dependency are joined in FIG. 22B bysolid lines, while instructions that exhibit an anti-dependence or anoutput dependence are joined by broken lines. In FIG. 22B, instruction4“mov R1,R0”, instruction5 “mov R2,R3”, and instruction6 “add R3,R0” arejoined in a Y shape, with instruction4 “mov R1,R0” being further joinedby a broken line to instruction3 “st R0,(mem2)”. In this dependencygraph, the arrows are interpreted as the output order that should berespected when issuing instructions from the instruction registersA231-D234 to the instruction decoders 33˜35.

A dependency graph may be generated according to a conventional method,such as that disclosed in the paper Instruction Scheduling in the TOBEYcompiler (R. J. Blainey, IBMJ.RES.DEVELOP. Vol 38 No. 5 September 1994).

The instruction rearranging unit 121 refers to the dependency graphgenerated by the dependency analyzing unit 120 and rearranges theinstructions in a basic block, assigning one or more instructions toeach parallel execution code. This rearranging by the instructionrearranging unit 121 is analogous to a game where branches are cut off atree. FIGS. 22A˜22F show the procedure of this branch-cutting game. Inthe game, the dependency graph generated by the dependency analyzingunit 120 is considered to be a tree whose branches are combinations ofnodes and edges. Nodes that are indicated by an edge but do notthemselves indicate any other edges (nodes 1, 5, and 8 in FIG. 22C) areconsidered to be the end branches.

In FIG. 22D, the player selects node 1 out of the end branches and cutsoff this node. Once node 1 has been removed, node 2 becomes an endbranch, so that the player next selects and cuts off one node out of theend branches nodes 2, 5, and 8. In FIG. 22E, the player selects node 8out of the end branches and cuts off this node.

The player continues to cut off branches as described above, with thenodes in the cut-off branches being arranged into a parallel executioncode in the order in which the nodes are cut off. An arrangement ofparallel execution codes that respects the dependencies in the programis obtained when all of the branches have been cut off the tree. Thelower the number of parallel execution codes, the higher the score ofthe player (which is to say, the better the parallel execution codes).This completes the description of the branch-cutting game as an analogyto the procedure for rearranging nodes.

The instruction rearranging unit 121 performs this rearranging inaccordance with the procedure in the flowchart shown in FIG. 23A. Inthis explanation, the expression “arranging” refers to the processingthat assigns up to three instructions in the four unit fields in aparallel execution code. An arrangement of instructions whose assignmentto a parallel execution code may be changed is called a provisionalarrangement, while an arrangement that will not be changed is called adefinite arrangement.

The expression “arrangement candidate” refers to a node that correspondsto an end branch in the branch-cutting game described above, which canbe a node that has no predecessors or a node whose predecessors have allbeen provisionally arranged. The nodes in the dependency graph that arecurrently arrangement candidates change as the process arranginginstructions into parallel execution codes progresses.

The following explanation describes each step in the arrangementprocess. In step S0, the instruction rearranging unit 121 sets thevariable i st “1”. This variable i indicates one of the parallelexecution codes included in the object program that will be generated bythe processing hereafter. In this example, each parallel execution codehas an initial length of 84 bits. The following step, step S1, forms aloop process (loop1) together with step S10. As a result, the processingin steps S2˜S9 is repeated for each node in the dependency graphgenerated by the dependency analyzing unit 120.

In step S2, the instruction rearranging unit 121 extracts all nodes thatare assignment candidates for a present parallel execution code from thedependency graph and forms an arrangement candidate group of such nodes.In the first iteration of loop1, nodes that have no predecessors areselected to form the arrangement candidate group.

Step S3˜S8 include loop statements (loop2) forming a loop thatdetermines which nodes in the arrangement candidate group formed in stepS2 should be assigned to a same parallel execution code. This loopprocess can end due to any of two circumstances. The first circumstanceis when all of the arrangement candidates in the arrangement candidategroup have been arranged into a parallel execution code so that noassignment candidates remain. This corresponds in the branch-cuttinggame to a case where there are few end branches (which is to say, thereare few arrangement candidates). There are cases where no assignmentcandidates remain after only one or two iterations of loop2. In suchcases, loop2 ends due to this first circumstance.

The second circumstance is where the four unit fields in the presentparallel execution code have been filled with arrangement candidates, sothat there is no more room in the parallel execution code. In thissecond circumstance, some of the arrangement candidates in thearrangement candidate group cannot be arranged into the parallelexecution code and so are left behind.

In step S9, the nodes that are to be arranged into the parallelexecution code are determined, regardless of which of the twocircumstances resulted in the exit from loop2. In detail, theinstructions that correspond to the nodes in the arrangement candidategroup are extracted from the original instruction sequence and parallelexecution boundaries are added by the parallel execution boundaryappending unit 122 shown in FIG. 21. When only one short instruction isdetermined as being arranged into the parallel execution code, in stepS9 a parallel execution boundary is set for this short instruction. Bydoing so, the parallel execution code is set as having a data length of21 bits. When one long instruction is determined as being arranged intothe parallel execution code, in step S9 a parallel execution boundary isset for this long instruction. By doing so, the parallel execution codeis set as having a data length of 42 bits. In the same way, when acombination of one short and one long instruction is determined as beingarranged into the parallel execution code, in step S9 a parallelexecution boundary is set for the long instruction in the combination.By doing so, the parallel execution code is set as having a data lengthof 63 bits.

When a short-short-long instruction combination is determined as beingarranged into the parallel execution code, in step S9 a parallelexecution boundary is set for the long instruction in the combination.By doing so, the parallel execution code is set as having a data lengthof 84 bits.

In step S1, variable is incremented by “1” so as to make it indicate thenext parallel execution code into which instructions are to be arranged.The processing then returns to step S10.

When the processing moves to step S2 in a second or later iteration ofloop1, the provisional arrangement of one of the instructions will bebeen completed. As a result, a node that has the provisionally arrangedinstruction as a predecessor can hereafter be selected as part of thearrangement candidate group.

When loop2 ends due to the second circumstance, the nodes that were notarranged and so were left behind are also selected as arrangementcandidates. This shows that the nodes in the dependency graph that areselected as arrangement candidates change according to which nodes havebeen provisionally arranged into a parallel execution code and to whichnodes could not be provisionally arranged into the parallel executioncode and so were left behind.

In loop2, the instruction rearranging unit 121 performs the processingdescribed below (steps S4-S7) for each arrangement candidate in thearrangement candidate group.

Step S4 corresponds to the player of the branch-cutting game selectingan end branch to cut. In step S4, the node that is considered to be themost suitable for arranging at the present time is taken from thearrangement candidate group. The instruction rearranging unit 121selects this most suitable node by heuristically selecting aninstruction whose arrangement is believed to cause the greatestreduction in execution time for all instructions in the basic block.Here, a node situated at an end of the branch in the dependency graphwith the longest total execution time is selected. When more than onenode (instruction) satisfy this criterion, the instruction that comesfirst in the original instruction sequence is selected.

In step S5, the instruction rearranging unit 121 judges whether the mostsuitable node can be arranged into the present parallel execution code,according to the procedure shown in FIG. 23B. When this is not possiblein steps S4˜S7 will be performed for a different assignment candidate inthe assignment candidate group.

When it is possible to arrange the most suitable node into the parallelexecution code, the processes moves from step S5 to step S6, theinstruction rearranging unit 121 judges whether there is sufficientspace in the 84-bit parallel execution code to arrange the presentarrangement candidate.

If not, the processing leaves loop2 and returns to step S9. If so, thejudgement “Yes” is made in step S6 and the processing advances to stepS7.

As a general rule, the processing in steps S4-S6 is repeated and theinstructions are progressively assigned to parallel execution codes. Itshould be noted here that even if there is still space in a parallelexecution code for the arrangement of another instruction, there willstill be cases where no instruction will be arranged due to there beingno more arrangement candidates. When there is only one assignmentcandidate, processing of all the assignment candidates will be completedby a single iteration of loop2, so that the processing will then returnto step S9. However, if nodes could somehow be added as assignmentcandidates when the number of assignment candidates is low, furtheriterations of loop2 would be possible. Nodes that have ananti-dependence or an output dependence with the most suitable node arenodes that were not selected as arrangement candidates in step S2 butwhich may be later added as assignment candidates. Such nodes cannot beexecuted before the most suitable node, but can be executed in the samecycle as the most suitable node. As a result, when the judgement “Yes”is given in the flowchart in FIG. 23A, the processing moves to step S7and nodes that have only the most suitable node that is presently beingarranged as a predecessor and have an anti- or an output dependence withthe most suitable node are added to the arrangement candidate group asarrangement candidates. After this, the processing moves to step S8 sothat the processing in steps S4-S7 is performed for the newly addedarrangement candidates.

The following describes method used in FIG. 5 to judge whetherarrangement is possible, with reference to the flowchart shown in FIG.23B.

In step U1, the instruction rearranging unit 121 checks whether theinstructions included in the present parallel execution code satisfy therestrictions set by the number of calculating resources. In detail, theinstruction rearranging unit 121 judges whether the processor will beable to simultaneously process the instruction being judged in additionto the instructions that have already been provisionally arranged intothe parallel execution code. If not possible, the instructionrearranging unit 121 judges that the present instruction cannot bearranged into the parallel execution code.

Next, in step U2, the instruction rearranging unit 121 judges whetherthe number of instructions that have already been provisionally arrangedinto the present parallel execution code is less than the number ofdecoders in the processor minus one. If so, the instruction rearrangingunit 121 judges that the present instruction can be arranged into theparallel execution code and the processing advances to step U9. In thisexample, the number of decoders provided in the processor of the firstembodiment is three, so that the judgement in step U2 is satisfied if 0or 1 instructions have been provisionally arranged. When this is thecase, the instruction presently being analyzed (also referred to as the“processed instruction”) will definitely fit into the parallel executioncode regardless of whether it is a short or long instruction, so thatthe processing proceeds to step U9.

When the number of instructions that have already been provisionallyarranged into the present parallel execution code is not less than thenumber of decoders in the processor minus one, the judgement “No” isgiven in step U2 and the processing proceeds to step U3. In step U3, thenumber of instructions that have already been provisionally arranged istwo, so that a judgement is performed to see whether both instructionsare short instructions. Here, when two short instructions have alreadybeen arranged into the parallel execution code i, the processedinstruction will definitely fit into the parallel execution code iregardless of whether it is a short instruction or a long instruction.This is because the target processor is capable of executing bothshort-short-short and short-short-long instruction combinations.Consequently, the processing advances to step U9.

In step U9, the processed instruction is provisionally arranged into theparallel execution code. When no instructions have yet been arrangedinto the parallel execution code i, the processed instruction isarranged into the first unit field in the parallel execution code. Wheninstructions have been arranged into the first-third unit fields of theparallel execution code i, the processed instruction is arranged intothe first open unit field in the parallel execution code i. In detail,when an instruction has already been arranged into the first unit field,the processed instruction is arranged into the second unit field.Conversely, when one or two instructions have already been arranged intothe first and second unit fields, the processed instruction is arrangedinto the third unit field.

When the judgement in step U3 is negative, the processing advances tostep U4. In step U4, the instruction rearranging unit 121 judges whetherthe instructions arranged into the first˜third unit fields in theparallel execution code i are a short-long instruction combination or along-short instruction combination. Here, if the provisionally arrangedinstructions are a long-long combination, it will not be possible for afurther instruction to be executed in parallel, so that the arrangementof the processed instruction is judged to be impossible. Conversely,when the provisionally arranged instructions are one of the twocombinations given above, the processing advances to step U5.

In step U5, the instruction rearranging unit 121 judges whether theprocessed instruction that it is trying to arrange is a shortinstruction. If the processed instruction is a long instruction,arrangement of this instruction will produce a long-short-long orshort-long-long instruction combination in the parallel execution codei, neither of which can be executed by the target processor.Consequently, the instruction rearranging unit 121 judges thatarrangement is impossible.

On finding that the processed instruction in step U5 is a shortinstruction, the instruction rearranging unit 121 uses the dependencygraph to analyze any dependencies between the processed instruction andinstructions in the program that have already been provisionallyarranged. Here, dependencies between the arrangement candidates areanalyzed because arrangement candidates may have been added in step S7in FIG. 23A. In detail, if the processed instruction is a node that wasadded in step S7, there is a possibility that this processed instructionwill have an anti-dependence or output dependence with one or more ofthe provisionally arranged instructions. In the example shown in FIG.22B, a broken-line edge is present between instruction3 “st R0, (mem2)”and instruction4 “mov R1,R0”, showing that an anti-dependence existsbetween these instructions. In this dependency graph, there will be noproblems if instruction3 “st R0,(mem2)”—instruction5 “mov R2,R3” areassigned to the unit fields of the parallel execution code i in theorder instruction3 “st R0,(mem2)”-instruction5 “mov R2,R3”-instruction4“mov R1,R0”. This is because even if the circumstances of the targetprocessor dictate that instruction3 “st R0,(mem2)” is executed in adifferent cycle to instruction5 “mov R2,R3” and instruction4 “movR1,R0”, instruction3 “st R0,(mem2)” will be executed first, withinstruction5 “mov R2,R3” and instruction4 “mov R1,R0” being executedlater. Consequently, the anti-dependence between the instructions isproperly maintained.

If instruction3 “st R0,(mem2)”˜instruction5 “mov R2,R3” are assigned tothe unit fields of the parallel execution code i in the orderinstruction4 “mov R1,R0” instruction5 “mov R2,R3”-instruction3 “stR0,(mem2), however, there is the risk that the anti-dependent will bebroken. This is because the circumstances of the target processor maydictate that instruction4 “mov R1,R0” is executed in a different cycleto instruction5 “mov R2,R3” and instruction3 “st R0,(mem2)”. If so,instruction4 “mov R1,R0” will be executed first, with instruction5 “movR2,R3” and instruction3 “st R0,(mem2)” being executed later. Thisresults in the anti-dependence being broken. In this way, when twoarrangement candidates that exhibit dependency are arranged into thesame parallel execution code, there is the risk of an anti-dependencebeing broken, so that the analysis of dependencies in step U6 isrequired.

In step U7, the instruction rearranging unit 121 refers to the resultsof the analysis performed in step U6 and judges whether it is possibleto rearrange the instructions that have been provisionally arranged andthe processed instruction to produce a short-short-long instructionarrangement. When there is no anti-dependence or output dependence inthe program between the processed instruction and the provisionallyarranged instructions, these instructions may be rearranged to produce ashort-short-long instruction arrangement, so that the instructionrearranging unit 121 rearranges the instructions in this way.Conversely, when there is anti-dependence or output dependence in theprogram between the processed instruction and the provisionally arrangedinstructions, a short-short-long arrangement where the anti- or outputdependence is not broken is selected. If the anti- or output dependenceis broken regardless of how the short instructions are arranged,arrangement of the processed instruction in the present parallelexecution code is judged to be impossible. If there is an arrangementwhere the dependency is not broken, the instruction are rearranged inaccordance with such arrangement.

Step U8 is performed if the judgement in step S7 is affirmative. Theinstruction rearranging unit 121 arranges the processed instruction andrearranges the provisionally arranged instructions into the alignmentthat satisfies the criteria judged in step U7.

Object Code Generating Unit 113

The following explanation returns to FIG. 21 to describe the componentsof the instruction conversion apparatus. The object code generating unit113 divides the parallel execution codes, which have been assignedinstructions and given parallel execution boundaries by the instructionscheduling unit 112, into packet units. The packet sequence that is madeup of the packets produced by this division are then stored in a file asrelocatable object codes and the resulting file is outputted.

Linking Unit 114

The linking unit 114 links a plurality of relocatable object codes thatwere generated in different compiling units to produce one linkedsequence, refers to symbol information and calculates the final addressof each label, and determines the size of each label. The symbolinformation referred to here is information showing the actual addressof the parallel execution code to which each label in the object code isassigned.

The linking unit 114 of the present invention differs from aconventional linker by including an address resolving unit 123. Theaddress resolving unit 123 resolves addresses in object code thatinclude unresolved addresses and can be realized by software theexecutes the procedure shown in FIG. 24.

FIG. 24 is a flowchart showing the procedure executed by the addressresolving unit 123 which forms part of the linking unit 114.

In step V0, the address resolving unit 123 extracts all instructions(hereafter called “unresolved instructions”) that include an unresolvedlabel from the object codes that have been assigned addresses. Step V10is a loop statement for having the processing in step V1-step V9repeated for each instruction extracted in step V0. In step V1, theaddress resolving unit 123 refers to the symbol information andcalculates a displacement to the branch or reference destination fromthe address of the unresolved instruction. When the address of theunresolved instruction is close to the branch or reference destination,a small value will be given as the displacement, while the address ofthe unresolved instruction is far from the branch or referencedestination, a large value will be given as the displacement.

Once the displacement has been calculated, the processing advances tostep V2, where the address resolving unit 123 judges whether thedisplacement can be expressed by a 5-bit value. If so, the processingadvances to step V3.

When the assembler codes are rearranged, instructions that includedisplacements are regarded as short instructions and are arranged intoparallel execution codes as such. When the displacement can be expressedby a 5-bit value, the displacement can be written into the operand of ashort instruction without causing any problems. As a result, thedetermined displacement is written into the unresolved instruction,thereby completing the processing of the present unresolved instruction.

On the other hand, when the determined displacement cannot be expressedby a 5-bit value, the displacement cannot be written into the operand ofa short instruction. As a result, the judgement “Yes” is given in stepV2 and the processing proceeds to step V4. In step V4, the addressresolving unit 123 judges whether the displacement cannot be expressedby a 21-bit value. If not, the judgement “No” is given and theprocessing advances to step V5. In other words, the displacement can bewritten as an operand if the unresolved instruction is converted to along instruction, so that in step V5, the instruction size of theunresolved instruction is increased to make the unresolved instruction along instruction, and the displacement is written in the longinstruction as a 21-bit value. Note that there can be cases where thisextension of an unresolved instruction results in the parallel executioncode including the unresolved instruction violating the restrictionsgoverning the possible combinations of instructions in a parallelexecution code, meaning that simultaneous execution will no longer bepossible for the instruction in the parallel execution code. As aresult, once an unresolved instruction has been extended to become along instruction, step V9 judges whether the parallel execution codestill satisfies one of the patterns in A˜H shown in FIG. 7. If this isnot the case, the processing proceeds to step V6 where a parallelexecution boundary is inserted before or after the unresolvedinstruction to ensure that parallel execution will still be possible.

When the calculated displacement cannot be expressed by a 21-bit value,the judgement “Yes” is given in step V4 and the processing proceeds tostep V7. When the calculated displacement exceeds 21 bits, thedisplacement cannot be written even if the unresolved instruction isexpanded to become a long instruction. In this case, the unresolvedinstruction is processed by replacing it with a long instruction (1) anda short instruction (2). The processing content of these instructions isas follows.

Long instruction (1): transfer instruction that transfers an addressinto a register.

Short instruction (2) instruction that executes the same processing asthe unresolved instruction in addressing mode using the register intowhich the address has been transferred.

The register that is used in addressing mode is specially reserved forthis division of instructions.

In step V7, there is a data dependency over the register between thelong instruction (1) and the short instruction (2) used to replace theunresolved instruction, meaning that these instructions cannot beexecuted simultaneously. Consequently, step V8 inserts a parallelexecution boundary between the long instruction (1) and the shortinstruction (2).

As a result of the above processing, even if the determination of anunresolved address in the linking process results in a change in thelength of instructions, it is still guaranteed that parallel executioncodes which can be executed by the target processor will be outputted.

As described above, when three instructions to be executed in parallelare composed of two short and one long instructions, the instructionconversion apparatus of the present invention rearranges theinstructions into a short-short-long instruction pattern. Since bothshort instructions and long instructions have their opcodes located inthe first instruction unit, the above instruction pattern has allopcodes arranged in the first three instruction units. In such case, thedecoders of the target processor can decode the first three units in aparallel execution code and so have the processor execute the maximum ofthree instructions in parallel.

Operation of the Processor

The following describes the operation of the processor of the firstembodiment when decoding and executing specific instructions.

FIG. 25 is a flowchart showing an example of a process that handles a32-bit constant.

In FIG. 25, the 32-bit constant “0×87654321” is transferred intoregister R1 (step S100). The stored value of register R5 is transferredto register R0 (step 101). The stored value of register R0 is added tothe stored value of register R1 (step S102). The stored value ofregister R3 is added to the stored value of register R2 (step S103). Thestored value of register R0 is stored at the address in the memory shownby the stored value of register R4 (step S104). The stored value ofregister R0 is transferred to register R6 (step S105). Finally, thestored value of register R3 is transferred to register R7 (step S106).

FIG. 26A shows an example of the executable codes in a program that hasthe present processor execute the processing shown in FIG. 25, and FIG.26B shows an execution image.

The program is composed of seven instructions. These instructions aresupplied in the three packets 70˜72. The processing in each instructionis expressed by the mnemonics located in each field of the executablecodes. As specific examples, the mnemonic “mov” represents the transferof a constant or the stored value of a register into a register, themnemonic “add” represents the addition of a constant or the stored valueof a register to the stored value of a register, and the mnemonic “st”represents the transfer of the stored value of a register into memory.

Note that constants are expressed in hexadecimal. Also, the expression“Rn (n=0-31)” indicates one of the registers in the register file 43.The parallel execution boundary information f10 and the formatinformation f11 are each expressed as “1” or “0”.

The following describes the operation of the processor for eachexecution unit shown in FIG. 26B when processing according to theflowchart shown in FIG. 25.

Execution Unit 1

Packet 70 is supplied from the memory, and the units in packet 70 aretransferred to the instruction register 23 in order. After this, theinstruction issuing control unit 31 refers to the parallel executionboundary information f10 and format information f11 of each unit andcontrols the issuing of instructions. In detail, the format informationf11 of the first unit is “1”, so that the instruction issuing controlunit 31 links the first unit and second unit and treats them as oneinstruction. The no operation instruction flag of the second instructiondecoder 34 is set at “1”, and the decoding of the second unit as aninstruction is invalidated. The parallel execution boundary informationf10 of the first unit is “0”, and the parallel execution boundaryinformation f10 of the third unit is “1”, so that the instructionissuing control unit 31 issues the first˜third units as twoinstructions. Since all of the supplied units are issued, no units areaccumulated in the instruction buffer 22.

The executing unit 40 transfers the constant “0×87654321” to register R1and transfers the stored value of register R5 to register R0.

Execution Unit 2

Packet 71 is supplied from memory, and the units in packet 71 aretransferred to the instruction register 23 in order. The formatinformation f11 of all three units is “0”, so that each unit forms a21-bit instruction. The parallel execution boundary information f10 ofthe first unit is “0”, and the parallel execution boundary informationf10 of the second unit is “1”, so that the instruction issuing controlunit 31 issues the first and second units as two instructions. The thirdunit is not issued and so is accumulated in the instruction buffer 22.

The executing unit 40 adds the stored value of register R0 to the storedvalue of register R1 and stores the result in register R0. The executingunit 40 also adds the stored value of register R3 to the stored value ofregister R2 and stores the result in register R3.

Execution Unit 3

Packet 72 is supplied from memory, and one unit accumulated in theinstruction buffer 22 and the two units in packet 72 are transferred tothe instruction register 23 in order. The format information f11 of allthree units is “0”, so that each unit forms a 21-bit instruction. Theparallel execution boundary information f10 of the first unit and thesecond unit is “0”, and the parallel execution boundary information f10of the third unit is “1”, so that the instruction issuing control unit31 issues all three units as three separate instructions. In this case,all of the supplied units are issued as instructions.

The executing unit 40 transfers the stored value of register R0 to theaddress in the memory shown by the stored value of register R4,transfers the stored value of register R0 to register R6, and transfersthe stored value of register R3 to register R7.

As described above, the program that has the present processor executethe processing shown in FIG. 25 in three execution units. The executablecodes are composed of one 42-bit instruction and 6 21-bit instructions,so that the total code size is 168 bits.

Supplementary Explanation for the Instruction Conversion Apparatus ofthe Second Embodiment

First Specific Example of the Operation of the Instruction ConversionApparatus

The following describes the operation of the characteristic componentsof the present instruction conversion apparatus, with reference tospecific instructions.

FIG. 27A shows assembler codes that are generated by the assembler codegenerating unit 111 when source codes are inputted into the compilerupstream part 110. The instruction scheduling unit 112 receives an inputof the codes shown in FIG. 25. The meaning of each instruction shown inFIG. 27A is as follows.

Instruction 1: the constant 0×1000 (“0×” showing that the value is inhexadecimal) is transferred to the register R0.

Instruction 2: the content of register R0 is stored in the memoryaddress indicated by the stack pointer SP.

Instruction 3: the content of register R1 is transferred to register R2.

Instruction 4: the content of register R3 is transferred to register R4.

Instruction 5: the content of register R2 is added to register R4.

The following explain the operation of the instruction scheduling unit112 with reference to FIGS. 27B˜27E. First, the dependency analyzingunit 120 is activated and the dependency graph shown in FIG. 27B isgenerated from the codes shown in FIG. 27A. Next, the instructionrearranging unit 121 is activated. When loop2 composed of steps S3˜S8ends, the processing moves to step S9 where the instruction rearrangingunit 121 determines a group including one or more instructions as thearranged nodes. The unit for determining such groups is called a“cycle”.

First Cycle

First, the arrangement candidate group is selected (step S2). At thispoint, the nodes with no predecessors are nodes 1, 3, and 4. Next, themost suitable node is selected (step S4). In this example, node 1 isselected. Next, it is judged whether node 1 can be arranged (step S5).In this example, arrangement of node 1 is judged possible (steps U1,U2), so that node 1 is provisionally arranged (step U9).

At this point, the parallel execution code is as shown on the top levelof FIG. 27C. Next, the arrangement state is judged (step S6). Since theparallel execution code at this point is as shown on the top level ofFIG. 27C, further arrangement is judged as being possible. Since no newarrangement candidates are generated (step S7), the processing returnsto the start of loop2 (step S8). Since there are still nodes remainingin the arrangement candidate group, loop2 is repeated (step S3). Next,the most suitable node is selected (step S4). In this example, node 3 isselected. Next, it is judged whether node 3 can be arranged (step S5).In this example, arrangement of node 3 is judged possible (steps U1,U2), so that node 3 is provisionally arranged (step U9).

At this point, the parallel execution code is as shown on the secondlevel of FIG. 27C. Next, the arrangement state is judged (step S6).Since the parallel execution code at this point is as shown on thesecond level of FIG. 27C, further arrangement is judged as beingpossible. Since no new arrangement candidates are generated (step S7),the processing returns to the start of loop2 (step S8). Since there arestill nodes remaining in the arrangement candidate group, loop2 isrepeated (step S3). Next, the most suitable node is selected (step S4).In this example, only node 4 is left, so this is selected. Next, it isjudged whether node 4 can be arranged (step S5). In this example, thepresent parallel execution code is as shown on the second level of FIG.27C, with two instructions having been provisionally arranged in along-short pattern. As a result, the processing advances to step U5 viasteps U1˜U4. The present processed instruction is a short instruction,so that the judgement “Yes” is given in step U5 and the processingadvances to step U6.

In step U6, dependencies between the provisionally arranged instruction(nodes 1 and 3) and the processed instruction (node 4) are investigated.As can be understood from the dependency graph, no dependency existsbetween these instructions, so that instructions 1, 3, and 4 may beexecuted in any order. As a result, the judgement “Yes” is given in stepU7, and the instructions in the present parallel execution code arerearranged into the order 3, 4, 1 in step U8. The arranged state is thenexamined (step S6). At this point, the parallel execution code is asshown by the third level in FIG. 27C, and since the number ofprovisionally assigned instructions has reached three, the maximumnumber of instructions that can be executed in parallel by the processorof the first embodiment, assignment of further instructions is judged tobe impossible. Accordingly, loop2 ends and the processing moves to stepS9. In step S9, the instruction that have been provisionally arrangedare confirmed as being arranged into the present parallel executioncode. At this point, the processing of the first cycle is complete.Since unassigned nodes remain, however, loop 1 is repeated (steps S10,S1).

Second Cycle

First, the arrangement candidate group is selected (step S2). At thispoint, the nodes with no predecessors, nodes 2 and 5, are set as theselection candidates. The following processing is the same as in thefirst cycle and so will not be explained. This processing in the secondcycle results in these two nodes being arranged as arrangedinstructions.

Next, the instruction rearranging unit 121 inserts a parallel executionboundary at the first instruction of each cycle. After these parallelexecution boundaries have been inserted, the codes are as shown in FIG.27D.

After this, the object code generating unit 113 is activated. In thepresent example, the codes shown in FIG. 27D are outputted as the objectfile.

Finally, the linking unit 114 is activated. Since address resolution isnot required for the codes shown in FIG. 27D, the final executable codesare obtained via the same processing as a conventional linker. An imageof the executable codes is shown in FIG. 27E. The actual executablecodes are bit sequences that have been divided into 64-bit units.

FIG. 28A shows assembler codes that are generated by the assembler codegenerating unit 111 when source codes are inputted into the compilerupstream part 110. The instruction scheduling unit 112 receives an inputof the codes shown in FIG. 28A. The meaning of each instruction shown inFIG. 28A is as follows.

Instruction 6: the content of the memory indicated by the label “mem1”is loaded into the register R0.

Instruction 7: the content of register R0 is stored in the memoryaddress indicated by the stack pointer SP.

Instruction 8: the content of register R1 is transferred to register R2.

Instruction 9: the content of register R3 is transferred to register R4.

Instruction 10: the content of register R2 is added to register R4.

First, the dependency analyzing unit 120 is activated and the dependencygraph shown in FIG. 28B is generated from the code shown in FIG. 28A.Next, the instruction rearranging unit 121 and the parallel executionboundary appending unit 122 are activated. The processing result for theinstruction scheduling unit 112 is transferred to the object codegenerating unit 113 and the resulting code shown in FIG. 28C isoutputted as the object file. This processing is the same as in thefirst embodiment, so only the result is given.

Next, the linking unit 114 is activated. The codes shown in FIG. 28Cinclude an unresolved address, so that the address resolving unit 123 inthe linking unit 114 is activated. First, in step V1, the addressresolving unit 123 determines the address, so that the address “0×F000”is determined as “mem1”. Since “0×F000” is a value that exceeds 21 bits,the judgement “Yes” is given in both step V2 and step V4, so that theprocessing advances to step V7. In step V7, the instruction“ld(mem1),R0” is divided in the instructions “mov mem1,R31” and “ld(R31),R0”. In this example, register R31 is the register that isreserved for use when the instruction conversion apparatus dividesinstructions. Here, the reason the instruction “ld(mem1),R0” is dividedis that the only instructions of the processor that can handle a 32-bitvalue are transfer instructions that transfer a value to a register,with there being no load instruction that can directly handle a 32-bitaddress. Next, in step V8, a parallel execution boundary is insertedbetween the instructions “mov mem1,R31” and “ld (R31),R0”. This resultsin the final executable codes being as shown in FIG. 28D.

Comparison with a Conventional Fixed-Length VLIW Processor

The following compares, for the processing shown in FIG. 25, theoperation of the present processor to the operation of a VLIW processorthat uses fixed-length instructions as one example of the conventionalart.

For a simple VLIW processor that issues a fixed number of instructionswith a fixed instruction length in each cycle, the setting ofinstruction length at a suitable value for the transfer of a 32-bitconstant to be indicated by one instruction will result in an extremelylarge increase in overall code size. As a result, instruction length isset at 32 bits, and the transfer of a 32-bit constant is performed bydividing it into two transfer instructions that each transfer 16 bits.

FIGS. 29A and 29B show an example of the executable codes in a programexecuted by a VLIW processor that executes instructions of a fixedlength of 32 bits and an execution image.

The program is composed of four packets 73˜76. As in FIG. 26A, theprocessing content of each field is shown using mnemonics. Here,however, the mnemonic “sethi” refers to the storing of a 16-bit constantin the upper 16 bits of a register and the mnemonic “setlo” refers tothe storing of a 16-bit constant in the lower 16 bits of a register. Themnemonic “NOP” refers to an instruction with no operation content.

As can be seen from comparing the executable codes in FIG. 29A with theexecution image in FIG. 29B, all instructions supplied in one cycle areissued in the same cycle under VLIW methods. In other words, three32-bit instructions are issued in each cycle. When no instructions thatcan be executed in parallel exist, NOP instructions must be inserted inadvance by software. Four NOP instructions are inserted in the presentexample, making a total of twelve 32-bit instructions and a total codesize of 384 bits. This is much larger than the code size of the codeused by the processor of the first embodiment.

Since the transfer of a 32-bit constant into a register is divided intotwo instructions, a new dependency is created, so that the number ofexecution units in increased to four. No matter how the instructions arerearranged, this number cannot be reduced. As a result, one moreexecution cycle is required than when the same processing is performedby the processor of the first embodiment.

Comparison With a Conventional Processor Where Parallel ExecutionBoundary Information is Present in Fixed-Length Instructions

The following compares, for the processing shown in FIG. 25, theoperation of the present processor to the operation of a processor withfixed-length instructions including information showing whether there isa parallel execution boundary as another example of the conventionalart.

This conventional art will be explained with reference to a model thatexecutes 32-bit instructions and a model that executes 40-bitinstructions. Like the VLIW method shown in FIG. 29, the model thatexecutes 32-bit instructions performs the transfer of a 32-bit constantusing two instructions. However, the model that executes 40-bitinstructions can perform operations including the transfer of a 32-bitvalue into a register using only one instruction.

FIGS. 30A and 30B show an example of the executable codes and anexecution image for a program executed by a processor that executesinstructions which have a fixed length of 32 bits and include parallelexecution boundary information.

The program is composed of eight instructions that are supplied as thethree packets 77-79. The processing in each instruction is shown by themnemonics that have been placed into each field of the executable codes.As in the VLIW method with 32-bit instructions that was shown in FIG.29, the transfer of a 32-bit constant into a register is performed in16-bit units by two instructions.

As can be seen from FIGS. 30A and 30B, the transfer of a 32-bit constantinto a register is performed in 16-bit units by two instructions, which,as with the VLIW method of FIG. 29, generates a new dependency. Thismeans that one more execution cycle is required than when the processorof the first embodiment is used.

Since no NOP instructions need to be inserted, the code size is equal tothat of the VLIW method shown in FIG. 29 minus the code sizeattributable to the NOP instructions. This means that eight 32-bitinstructions are used, making the total code size 256 bits. However,this is still larger that the code size of the code used by theprocessor of the first embodiment.

The following compares the processor of the first embodiment to a modelthat uses instructions of a fixed length of 40 bits.

FIGS. 31A and 31B show an example of the executable codes and anexecution image for a program executed by a processor that executesinstructions which have a fixed length of 40 bits and include parallelexecution boundary information.

The program is composed of seven instructions that are supplied as thethree packets 80˜82. The processing in each instruction is shown by themnemonics that have been placed into each field of the executable codes.Here, the transfer of a 32-bit constant into a register can be performedby one instruction.

As can be seen from FIGS. 31A and 31B, the transfer of a 32-bit constantinto a register is performed by one instruction. This means that a totalof three execution cycles are required, which is the same as when theprocessor of the first embodiment is used.

While this conventional art uses the same number of instructions as theprocessor of the first embodiment, the conventional processor has aninstruction length of 40 bits which is used for all instructions. Theprocessor of the first embodiment has instructions that do not require alarge number of bits defined as 21-bit instructions. The program for theconventional processor is composed of seven 40-bit instructions, givinga total code size of 280 bits. This is larger than the code used by theprocessor of the first embodiment.

The processor of the present embodiment has been above by way ofembodiments, although the processor should not be construed as beinglimited to these embodiments. Several example modifications are givenbelow.

-   -   (1) The above embodiments use a premise that scheduling is        performed statically, although this is not a limitation for the        present invention. In other words, the present invention can        also be adopted by a processor that dynamically schedules        instructions, such as a superscalar processor. When doing so,        parallel execution boundary information is not provided in the        instructions, and the decoder is provided with a parallel        execution investigating apparatus for dynamically investigating        whether instructions can be executed in parallel. The control in        the above embodiments that was performed by the instruction        issuing control unit referring to the parallel execution        boundary information can be performed by referring to the output        of the parallel execution investigating apparatus. Such a        construction reduces the amount of hardware used by a processor        executing variable length instructions, thereby maintaining the        effect of the present invention.    -   (2) The above embodiments describe the case where a maximum of        three instructions are executed simultaneously, although the        present invention is not limited to this number. As one example,        a construction where two instructions are simultaneously issued        may be used. When doing so, suitable changes only need to be        made to the construction of the decoding unit and periphery of        the instruction register, and to the calculators in the        executing unit.    -   (3) As can be seen from the instruction formats given in FIGS.        6A˜6F, the above embodiments handle instructions that are        composed of one or two units. However, this is not a restriction        for the present invention, so that instruction formats where        three or more units are linked to form one instruction may also        be defined. As one example, when instructions are composed of up        to four instruction units, two bits can be used as the format        information of each instruction.    -   (4) As can be seen from the instruction formats given in FIGS.        6A˜6F, the above embodiments handle instructions that are        composed of one or two units. However, instructions composed of        a single unit do not need to be used. As an alternative example,        one instruction may be composed of two or three units. In such        case, only the wiring between the instruction register, the        instruction decoder, and the constant operand needs to be        changed.    -   (5) As can be seen from the instruction formats given in FIGS.        6A˜6F, the instructions described in the above embodiments        include information showing whether there is a parallel        execution boundary. This information may not be provided,        however. In such case, instructions only include format        information, and a NOP instruction is inserted whenever no        instruction that cannot be executed in parallel is present. In        such an arrangement, the major effect of the present invention,        namely, the ability to indicate instructions using an        instruction format of only the necessary length is still        achieved.    -   (6) As can be seen from the instruction formats shown in FIGS.        6A˜6F, the above embodiments describe a case where only part of        a constant operand can be positioned in the second of the two        units used to compose a 42-bit instruction, although an opcode        may alternatively be positioned into this unit. As a result, the        construction shown in FIG. 5 may be changed so that the unit        that was directly outputted as part of the constant operand may        be inputted into the instruction decoder, and the input bit        width of the instruction decoder may be increased.    -   (7) In the above embodiments, the instruction buffer was        described as having the construction shown in FIG. 8, although        the present invention is not restricted to this construction or        to this buffer size. As one example, one instruction buffer with        a simple queue structure may be used.    -   (8) Software that achieves the functioning of the instruction        conversion apparatus described in the second embodiment may be        distributed having been stored on a recording medium such as a        floppy disk, a hard disk, a CD-ROM, an MO (Magnetic-Optical)        disc, or a DVD (Digital Versatile Disc).

The executable program generated by the instruction conversion apparatusof the above embodiments of the present invention may be distributedhaving been recorded onto a floppy disk, a hard disk, a CD-ROM, an MOdisc, a DVD, or a semiconductor memory.

Although the present invention has been fully described by way ofexamples with reference to accompanying drawings, it is to be noted thatvarious changes and modifications will be apparent to those skilled inthe art. Therefore, unless such changes and modifications depart fromthe scope of the present invention, they should be construed as beingincluded therein.

1. An instruction conversion apparatus that converts an instruction sequence into parallel execution codes that are executable by a target processor, the target processor having predetermined limitations regarding combinations of instructions capable of being executed in parallel, the instruction conversion apparatus comprising: assigning means for successively assigning instructions in the instruction sequence to parallel execution codes; and control means for controlling the assigning means so that a combination of a plurality of instructions that have already been assigned to a parallel execution code and an instruction that the assigning means is about to assign to the parallel execution code satisfy the predetermined limitations of the target processor; wherein the target processor includes (1) a fetch means for successively fetching parallel execution codes that each include a plurality of unit fields from outside the target processor, (2) s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch means, (3) decoding means, including s decoders that correspond to 1^(st) to s^(th) registers in the s+k−1 registers, the decoders decoding at least one opcode stored in any of the 1^(st) to s^(th) registers, and (4) operation executing means, connected to the s+k−1 registers for executing operations in accordance with a decoding result of the s decoders, the assigning means assigning, when instructions to be assigned to a parallel execution code include a long instruction whose word length is equal to at least two but no more than k unit fields, one of an opcode and an operand of the long instruction to a u^(th) (where u is any integer such that 1<u<s) unit field between the 1^(st) unit field and the s^(th) unit field, and only an operand of the long instruction to unit fields from a (u+1)^(th) unit field to (u+k−1)^(th) unit field.
 2. The instruction conversion apparatus of claim 1, further comprising: grouping means for forming an instruction group of a plurality of instructions that do not exhibit a dependency relation (hereafter “data dependency relation”), a data dependency relation being a relation between an instruction defining a resource and an instruction referring to the same resource; and first detecting means for detecting, when a 1^(st) to an s^(th) unit field in a parallel execution code have been assigned at least one instruction by the assigning means and an instruction (hereafter “short instruction”) with a shorter word length than a long instruction is left in the instruction group, a long instruction assigned to unit fields between the 1^(st) unit field and the s^(th) unit field, wherein the control means includes a first control unit for controlling the assigning means to rearrange instructions that have already been assigned to the parallel execution code so that the detected long instruction is assigned to unit fields between the s^(th) unit field and the (s+k−1)^(th) unit field and the short instruction remaining in the instruction group is assigned to a unit field between the 1^(st) unit field and the (s−1)^(th) unit field.
 3. The instruction conversion apparatus of claim 2, wherein the instruction group includes instructions that exhibit an anti-dependence and instructions that exhibit an output dependence, an anti-dependence being a relation between an instruction that refers to a resource and an instruction that thereafter defines the resource, and an output dependence being a relation between an instruction that defines a resource and another instruction that defines the resource, the control means including a search unit for searching for a combination pattern, composed of a plurality of instructions in the instruction group, that is unaffected by an anti-dependence and an output dependence, and the first control unit controlling the assigning means to rearrange the plurality of instructions in accordance with the combination pattern found by the search unit, to assign the long instruction found by the detecting means to unit fields from the s^(th) unit field to the (s+k−1)^(th) unit field, and to assign a short instruction left in the instruction group to a unit field between the 1^(st) unit field and the (s−1)^(th) unit field.
 4. The instruction conversion apparatus of claim 3, further comprising: flag setting means for setting a parallel execution boundary flag at each boundary that marks a position at which the predetermined limitations of the target processor dictate that parallel execution is not possible.
 5. The instruction conversion apparatus of claim 4, further comprising: address resolving means for assigning a real address to a parallel execution code; and second detecting means for detecting, when a real address has been assigned to a parallel execution code, an instruction including the real address that is not capable of being expressed by an original word length of the instruction, the flag setting means setting the boundary flag at a unit field located one of before and after unit fields to which the instruction detected by the second detecting means has been assigned.
 6. The instruction conversion apparatus of claim 5, further comprising: replacing means for replacing an instruction detected by the second detecting means with a transfer instruction that transfers an address to a register and an addressing instruction that performs the same processing as the replaced instruction using the register, the assigning means assigning the two instructions substituted by the replacing means to a plurality of unit fields, and the flag setting means setting a boundary flag at one of the plurality of unit fields to which the two substituted instructions have been assigned to show a parallel execution boundary.
 7. A processor, comprising: fetch means for successively fetching parallel execution codes that include a plurality of unit fields from outside the processor; a register set for storing a combination of a plurality of instructions included in at least two parallel execution codes that have been fetched by the fetch means; decoding means for decoding, when the combination of instructions stored in the register set satisfies predetermined restrictions, the instructions in the combination in parallel; and operation execution means for executing a plurality of operations in parallel in accordance with a decoding result of the decoding means; s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch means, the decoding means including a decoders that correspond to 1^(st) to s^(th) registers in the s+k−1 registers and decode at least one opcode stored in any of the 1^(st) to s^(th) registers, and the operation executing means being connected to the s+k−1 registers and executing operations in accordance with a decoding result of the s decoders.
 8. The processor of claim 7, wherein a long instruction whose word length is equal to at least two but no more than k unit fields is stored in any of the s+k−1 registers with a first of the at least two but no more than k unit fields storing an opcode of the long instruction, the decoding means including: a decoding control unit which, when an opcode of a long instruction in stored in a u^(th) (1<u<s) unit field between the 1^(st) unit field the s^(th) unit field, has the u^(th) decoder decode the opcode stored in the u^(th) register and a value stored between the u^(th) register and the (u+k−1)^(th) register outputted to the operation execution means as an operand of the long instruction.
 9. The processor of claim 7, wherein the first unit field that stores the opcode of the long instruction has a format flat set at ON to show that the unit field forms part of a long instruction, the decoding control unit detecting a register that stores a unit field whose format flag is set at ON as the u^(th) register, and the decoding control unit having the uth decoder decode an operand stored in the u^(th) register and having a stored value between the u^(th) register and the (u+k−1)^(th) register outputted to the operation execution means as an operand of the long instruction.
 10. The processor of claim 7, wherein the decoding control unit performs control to invalidate a decoding operation of every decoder from the (u+1)^(th) decoder onwards when a value stored between the (u+1)^(th) register and the (u+k−1)^(th) register is outputted to the operation execution means as an operand of a long instruction.
 11. A recording medium storing executable code for a processor, the processor including (1) a fetch means for successively fetching parallel execution codes that each include a plurality of unit fields from outside the target processor, (2) s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch means, (3) decoding means, including a decoders that correspond to 1^(st) to s^(th) registers in the s+k−1 registers, the decoders decoding at least one opcode stored in any of the 1^(st) to s^(th) registers, and (4) operation executing means, connected to the s+k−1 registers for executing operations in accordance with a decoding result of the s decoders, the executable code stored on the recording medium being arranged such that at least one of an opcode and an operand of a long instruction having a word length of at least two but no more than k unit fields is arranged into a u^(th) (where u is any integer such that 1≦u≦s) into to a u^(th) (where u is any integer such that 1≦u≦s) unit field between the 1^(st) unit field and the s^(th) unit field, and only an operand of the long instruction is arranged in unit fields from a (u+1)^(th) unit field to a (u+k−1)^(th) unit field.
 12. A computer-readable recording medium storing an instruction conversion program that converts an instruction sequence into parallel execution codes that are executable by a target processor, the target processor having predetermined limitations regarding combinations of instructions that can be executed in parallel, the instruction conversion program comprising: an assigning step for successively assigning instructions in the instruction sequence to parallel execution codes; and a control step for controlling the assigning step so that a combination of a plurality of instructions that have already been assigned to a parallel execution code and an instruction that the assigning step is about to assign to the parallel execution code satisfy the predetermined limitations of the target processor; wherein the target processor includes (1) a fetch means for successively fetching parallel execution codes that each include a plurality of unit fields from outside the target processor, (2) s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch means, (3) decoding means, including a decoders that correspond to 1^(st) to s^(th) registers in the s+k−1 registers, the decoders decoding at least one opcode stored in any of the 1^(st) to s^(th) registers, and (4) operation executing means, connected to the s+k−1 registers for executing operations in accordance with a decoding result of the s decoders, the assigning step assigning, when instructions to be assigned to a parallel execution code include a long instruction whose word length is equal to at least two but no more than k unit fields, at least one of an opcode and an operand of the long instruction to a u^(th) (where u is any integer such that 1<u<s) unit field between the 1^(st) unit field the s^(th) unit field, and only an operand of the long instruction to unit fields from a (u+1)^(th) unit field to a (u+k−1)^(th) unit field.
 13. The computer-readable recording medium of claim 12, wherein the instruction conversion program further comprises: a grouping step for forming an instruction group of a plurality of instructions that do not exhibit a dependency relation (hereafter “data dependency relation”), a data dependency relation being a relation between an instruction defining a resource and an instruction referring to the same resource; and a first detecting step for detecting, when a 1^(st) to an s^(th) unit field in a parallel execution code have been assigned at least one instruction by the assigning step and an instruction (hereafter “short instruction”) with a shorter word length than a long instruction is left in the instruction group, a long instruction assigned to unit fields between the 1^(st) unit field and the s^(th) unit field, wherein the control step includes a first control substep for controlling the assigning step to rearrange instructions that have already been assigned to the parallel execution code so that the detected long instruction is assigned to unit fields between the s^(th) unit field and the (s+k−1)^(th) unit field and the short instruction remaining in the instruction group is assigned to a unit field between the 1^(st) unit field and the (s−1)^(th) unit field.
 14. The computer-readable recording medium of claim 13, wherein the instruction group includes instructions that exhibit an anti-dependence and instructions that exhibit an output dependence, an anti-dependence being a relation between an instruction that refers to a resource and an instruction that thereafter defines the resource, and an output dependence being a relation between an instruction that defines a resource and another instruction that defines the resource, the control step including a search substep for searching for a combination pattern, composed of a plurality of instructions in the instruction group, that is unaffected by an anti-dependence and an output dependence, and the first control substep controlling the assigning step to rearrange the plurality of instructions in accordance with the combination pattern found by the search substep, to assign the long instruction found by the detecting step to unit fields from the s^(th) unit field to the (s+k−1) unit field, and to assign a short instruction left in the instruction group to a unit field between the 1^(st) unit field and the (s−1)^(th) unit field.
 15. The computer-readable recording medium of claim 14, wherein the instruction conversion program further comprises: a flag setting step for setting a parallel execution boundary flag at each boundary that marks a position at which the predetermined limitations of the target processor dictate that parallel execution is not possible.
 16. The computer-readable recording medium of claim 15, wherein the instruction conversion program further comprises: an address resolving step for assigning a real address to a parallel execution code; and a second detecting step for detecting, when a real address has been assigned to a parallel execution code, an instruction including the real address that cannot be expressed by an original word length of the instruction, the flag setting step setting the boundary flag at a unit field located one of before and after unit fields to which the instruction detected by the second detecting step has been assigned.
 17. The computer-readable recording medium of claim 16, wherein the instruction conversion program further comprises: a replacing step for replacing an instruction detected by the second detecting step with a transfer instruction that transfers an address to a register and an addressing instruction that performs the same processing as the replaced instruction using the register, the assigning step assigning the two instructions substituted by the replacing step to a plurality of unit fields, and the flag setting step setting a boundary flag at one of the plurality of unit fields to which the two substituted instructions have been assigned to show a parallel execution boundary.
 18. An instruction conversion apparatus that converts an instruction sequence into parallel execution codes that are executable by a target processor, the target processor having predetermined limitations regarding combinations of instructions capable of being executed in parallel, the instruction conversion apparatus comprising: an assigning unit for successively assigning instructions in the instruction sequence to parallel execution codes; and a control unit for controlling the assigning unit so that a combination of a plurality of instructions that have already been assigned to a parallel execution code and an instruction that the assigning unit is about to assign to the parallel execution code satisfy the predetermined limitations of the target processor; wherein the target processor includes (1) a fetch unit for successively fetching parallel execution codes that each include a plurality of unit fields from outside the target processor, (2) s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch unit, (3) a decoding unit, including a decoders that correspond to 1^(st) to s^(th) registers in the s+k−1 registers, the decoders decoding at least one opcode stored in any of the 1^(st) to s^(th) registers, and (4) an operation executing unit, connected to the s+k−1 registers for executing operations in accordance with a decoding result of the s decoders, the assigning unit assigning, when instructions to be assigned to a parallel execution code include a long instruction whose word length is equal to at least two but no more than k unit fields, one of an opcode and an operand of the long instruction to a u^(th) (where u is any integer such that 1<u<s) unit field between the 1^(st) unit field and the s^(th) unit field, and only an operand of the long instruction to unit fields from a (u+1)^(th) unit field to a (u+k−1)^(th) unit field.
 19. The instruction conversion apparatus of claim 18, further comprising: a grouping unit for forming an instruction group of a plurality of instructions that do not exhibit a dependency relation (hereafter “data dependency relation”), a data dependency relation being a relation between an instruction defining a resource and an instruction referring to the same resource; and a first detecting unit for detecting, when a 1^(st) to an s^(th) unit field in a parallel execution code have been assigned at least one instruction by the assigning unit and an instruction (hereafter “short instruction”) with a shorter word length than a long instruction is left in the instruction group, a long instruction assigned to unit fields between the 1^(st) unit field and the s^(th) unit field, wherein the control unit includes a first control unit for controlling the assigning unit to rearrange instructions that have already been assigned to the parallel execution code so that the detected long instruction is assigned to unit fields between the s^(th) unit field and the (s+k−1)^(th) unit field and the short instruction remaining in the instruction group is assigned to a unit field between the 1^(st) unit field and the (s−1)^(th) unit field.
 20. The instruction conversion apparatus of claim 19, wherein the instruction group includes instructions that exhibit an anti-dependence and instructions that exhibit an output dependence, an anti-dependence being a relation between an instruction that refers to a resource and an instruction that thereafter defines the resource, and an output dependence being a relation between an instruction that defines a resource and another instruction that defines the resource, the control unit including a search unit for searching for a combination pattern, composed of a plurality of instructions in the instruction group, that is unaffected by an anti-dependence and an output dependence, and the first control unit controlling the assigning unit to rearrange the plurality of instructions in accordance with the combination pattern found by the search unit, to assign the long instruction found by the detecting unit to unit fields from the s^(th) unit field to the (s+k−1)^(th) unit field, and to assign a short instruction left in the instruction group to a unit field between the 1^(st) unit field and the (s−1)^(th) unit field.
 21. The instruction conversion apparatus of claim 20, further comprising: a flag setting unit for setting a parallel execution boundary flag at each boundary that marks a position at which the predetermined limitations of the target processor dictate that parallel execution is not possible.
 22. The instruction conversion apparatus of claim 21, further comprising: an address resolving unit for assigning a real address to a parallel execution code; and a second detecting unit for detecting, when a real address has been assigned to a parallel execution code, an instruction including the real address that is not capable of being expressed by an original word length of the instruction, the flag setting unit setting the boundary flag at a unit field located one of before and after unit fields to which the instruction detected by the second detecting unit has been assigned.
 23. The instruction conversion apparatus of claim 22, further comprising: a replacing unit for replacing an instruction detected by the second detecting unit with a transfer instruction that transfers an address to a register and an addressing instruction that performs the same processing as the replaced instruction using the register, the assigning unit assigning the two instructions substituted by the replacing unit to a plurality of unit fields, and the flag setting unit setting a boundary flag at one of the plurality of unit fields to which the two substituted instructions have been assigned to show a parallel execution boundary.
 24. A processor, comprising: a fetch unit for successively fetching parallel execution codes that include a plurality of unit fields from outside the processor; a register set for storing a combination of a plurality of instructions included in at least two parallel execution codes that have been fetched by the fetch unit; a decoding unit for decoding, when the combination of instructions stored in the register set satisfies predetermined restrictions, the instructions in the combination in parallel; and an operation execution unit for executing a plurality of operations in parallel in accordance with a decoding result of the decoding unit; s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch unit, the decoding unit including a decoders that correspond to 1^(st) to s^(th) registers in the s+k−1 registers and decode at least one opcode stored in any of the 1^(st) to s^(th) registers, and the operation executing unit being connected to the s+k−1 registers and executing operations in accordance with a decoding result of the s decoders.
 25. The processor of claim 24, wherein a long instruction whose word length is equal to at least two but no more than k unit fields is stored in any of the s+k−1 registers with a first of the at least two but no more than k unit fields storing an opcode of the long instruction, the decoding unit including: a decoding control unit which, when an opcode of a long instruction in stored in a u^(th) (1<u<s) unit field between the 1^(st) unit field the s^(th) unit field, has the u^(th) decoder decode the opcode stored in the u^(th) register and a value stored between the u^(th) register and the (u+k−1)^(th) register outputted to the operation execution unit as an operand of the long instruction.
 26. The processor of claim 24 wherein the decoding control unit performs control to invalidate a decoding operation of every decoder from the (u+1)^(th) decoder onwards when a value stored between the (u+1)^(th) register and the (u+k−1)^(th) register is outputted to the operation execution unit as an operand of a long instruction.
 27. A recording medium storing executable code for a processor, the processor including (1) a fetch unit for successively fetching parallel execution codes that each include a plurality of unit fields from outside the target processor, (2) s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch unit, (3) a decoding unit, including a decoders that correspond to 1^(st) to s^(th) registers in the s+k−1 registers, the decoders decoding at least one opcode stored in any of the 1^(st) to s^(th) registers, and (4) an operation executing unit, connected to the s+k−1 registers for executing operations in accordance with a decoding result of the s decoders, the executable code stored on the recording medium being arranged such that at least one of an opcode and an operand of a long instruction having a word length of at least two but no more than k unit fields is arranged into to a u^(th) (where u is any integer such that 1<u<s) unit field between the 1^(st) unit field and the s^(th) unit field and the s^(th) unit field, and only an operand of the long instruction is arranged in unit fields from a (u+1)^(th) unit field to a (u+k−1)^(th) unit field.
 28. A computer-readable recording medium storing an instruction conversion program that converts an instruction sequence into parallel execution codes that are executable by a target processor, the target processor having predetermined limitations regarding combinations of instructions that can be executed in parallel, the instruction conversion program comprising: an assigning step for successively assigning instructions in the instruction sequence to parallel execution codes; and a control step for controlling the assigning step so that a combination of a plurality of instructions that have already been assigned to a parallel execution code and an instruction that the assigning step is about to assign to the parallel execution code satisfy the predetermined limitations of the target processor; wherein the target processor includes (1) a fetch unit for successively fetching parallel execution codes that each include a plurality of unit fields from outside the target processor, (2) s+k−1 (where s,k are integers no smaller than 2) registers for storing s+k−1 unit fields included in at least two parallel execution codes that have been fetched by the fetch unit, (3) a decoding unit, including s decoders that correspond to 1^(st) to s^(th) registers in the s+k−1 registers, the decoders decoding at least one opcode stored in any of the 1^(st) to s^(th) registers, and (4) an operation executing unit, connected to the s+k−1 registers for executing operations in accordance with a decoding result of the s decoders, the assigning step assigning, when instructions to be assigned to a parallel execution code include a long instruction whose word length is equal to at least two but no more than k unit fields, at least one of an opcode and an operand of the long instruction to a u^(th) (where u is any integer such that 1<u<s) unit field between the 1^(st) unit field the s^(th) unit field, and only an operand of the long instruction to unit fields from a (u+1)^(th) unit field to a (u+k−1)^(th) unit field.
 29. The computer-readable recording medium of claim 28, wherein the instruction conversion program further comprises: a grouping step for forming an instruction group of a plurality of instructions that do not exhibit a dependency relation (hereafter “data dependency relation”), a data dependency relation being a relation between an instruction defining a resource and an instruction referring to the same resource; and a first detecting step for detecting, when a 1^(st) and an s^(th) unit field in a parallel execution code have been assigned at least one instruction by the assigning step and an instruction (hereafter “short instruction”) with a shorter word length than a long instruction is left in the instruction group, a long instruction assigned to unit fields between the 1^(st) unit field and the s^(th) unit field, wherein the control step includes a first control substep for controlling the assigning step to rearrange instructions that have already been assigned to the parallel execution code so that the detected long instruction is assigned to unit fields between the s^(th) unit field and the (s+k−1)^(th) unit field and the short instruction remaining in the instruction group is assigned to a unit field between the 1^(st) unit field and the (s−1)^(th) unit field.
 30. The computer-readable recording medium of claim 29, wherein the instruction group includes instructions that exhibit an anti-dependence and instructions that exhibit an output dependence, an anti-dependence being a relation between an instruction that refers to a resource and an instruction that thereafter defines the resource, and an output dependence being a relation between an instruction that defines a resource and another instruction that defines the resource, the control step including a search substep for searching for a combination pattern, composed of a plurality of instructions in the instruction group, that is unaffected by an anti-dependence and an output dependence, and the first control substep controlling the assigning step to rearrange the plurality of instructions in accordance with the combination pattern found by the search substep, to assign the long instruction found by the detecting step to unit fields from the s^(th) unit field to the (s+k−1)^(th) unit field, and to assign a short instruction left in the instruction group to a unit field between the 1^(st) unit field and the (s−1)^(th) unit field.
 31. The computer-readable recording medium of claim 30, wherein the instruction conversion program further comprises: a flag setting step or setting a parallel execution boundary flag at each boundary that marks a position at which the predetermined limitations of the target processor dictate that parallel execution is not possible.
 32. The computer-readable recording medium of claim 31, wherein the instruction conversion program further comprises: an address resolving step for assigning a real address to a parallel execution code; and a second detecting step for detecting, when a real address has been assigned to a parallel execution code, an instruction including the real address that cannot be expressed by an original word length of the instruction, the flag setting step setting the boundary flat at a unit field located one of before and after unit fields to which the instruction detected by the second detecting step has been assigned.
 33. The computer-readable recording medium of claim 32, wherein the instruction conversion program further comprises: a replacing step for replacing an instruction detected by the second detecting step with a transfer instruction that transfers an address to a register and an addressing instruction that performs the same processing as the replaced instruction using the register, the assigning step assigning the two instructions substituted by the replacing step to a plurality of unit fields, and the flag setting step setting a boundary flag at one of the plurality of unit fields to which the two substituted instructions have been assigned to show a parallel execution boundary.
 34. A processor comprising: an execution unit which executes up to N number of instructions having a variable bit length in parallel, N being an integer which is at least two, wherein the maximum bit length of an instruction that is executed in parallel is M bits, M being an integer; an instruction supplying/issuing unit which fetches an instruction sequence in a unit of a first bit length of code and outputs the instruction sequence in a unit of a second bit length of code; a decoding unit which decodes the instruction sequence in a unit of a variable bit length of code which is at least a part of the second bit length of code outputted by the instruction supplying/issuing unit, and outputting a decoding result to the execution unit; and an instruction bus formed between the instruction supplying/issuing unit and the decoding unit, wherein the total bit width of the instruction bus is shorter than M*N bits, wherein the decoding unit decodes a plurality of instructions executed in parallel, and all of the instructions decoded in parallel at the same cycle pass through the instruction bus.
 35. The processor of claim 34, wherein the instruction sequence is converted by a certain instruction conversion apparatus.
 36. The processor of claim 35, wherein the instruction sequence is written in a high-level language before being converted by the instruction conversion apparatus.
 37. The processor of claim 34, wherein the first bit length is shorter than the second bit length.
 38. The processor of claim 34, wherein at least a part of the instructions have a special bit which instructs the processor to execute a plurality of instructions in parallel.
 39. The processor of claim 34, wherein the decoding unit comprises: an instruction issuing control unit which identifies instruction boundaries executed in parallel.
 40. The processor of claim 34, wherein the instruction supplying/issuing unit comprises: a fetch unit for successively fetching the instruction sequence; and a plurality of instruction buffers for temporally storing instructions.
 41. A processor comprising: an instruction fetching unit that fetches instructions, each instruction having a variable bit length, wherein the maximum bit length of an instruction that is executed in parallel is M bits, M being an integer; a decoding unit that decodes a plurality of instructions executed in parallel; an execution unit that executes up to N number of decoded instructions from the decoding unit in parallel, N being an integer which is at least two; and an instruction bus formed between the instruction fetching unit and the decoding unit, wherein the total bit width of the instruction bus is shorter than M*N bits, wherein the total bit length of the decoded instructions that are executed in parallel is variable which is not related to the bit length of the fetched instructions, and all of the instructions decoded in parallel at the same cycle pass through the instruction bus.
 42. The processor of claim 41, wherein the instruction are converted by a certain instruction conversion apparatus.
 43. The processor of claim 42, wherein the instructions are written in a high-level language before being converted by the instruction conversion apparatus.
 44. The processor of claim 41, wherein the instruction fetching unit fetches an instruction sequence in a unit of a first bit length of code and outputs the instruction sequence in a unit of a second bit length of code, the first bit length being shorter than the second bit length.
 45. The processor of claim 41, wherein at least a part of the instructions have a special bit which instructs the target processor to execute a plurality of instructions in parallel.
 46. The processor of claim 41, wherein the decoding unit comprises: an instruction issuing control unit which identifies instruction boundaries executed in parallel.
 47. The processor of claim 41, further comprising: a plurality of operation execution units capable of executing a plurality of instructions in parallel in accordance with a decoding result of the decoding unit.
 48. The processor of claim 41, wherein the instruction fetching unit comprises: a fetch unit for successively fetching the instruction sequence; and a plurality of instruction buffers for temporally storing instructions.
 49. The processor of claim 34, wherein the decoding result directly controls the execution unit.
 50. The processor of claim 41, wherein the decoding result directly controls the execution unit. 